TMS320C6421_17 Datasheet, PDF (37/222 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346D – JANUARY 2007 – REVISED JUNE 2008
Table 2-15. EMAC (MII/RMII) and MDIO Terminal Functions
SIGNAL
NAME
ZWT
NO.
HCNTL1/MTXEN/
GP[75]
D3
HD15/MTXCLK/
GP[73]
A4
HD9/MCOL/
GP[67]
C6
HD11/MTXD3/
GP[69]
C5
HD12/MTXD2/
GP[70]
D5
HD13/MTXD1/
GP[71]
B4
HD14/MTXD0/
GP[72]
D4
HR/W/MRXCLK/
GP[77]
A3
HHWIL/MRXDV/
GP[74]
C4
HCNTL0/MRXER/
GP[76]
B3
HD10/MCRS/
GP[68]
B5
HINT/MRXD3/
GP[82]
C2
HRDY/MRXD2/
GP[80]
D2
HDS1/MRXD1/
GP[79]
B2
HDS2/MRXD0/
GP[78]
C3
RMCRSDV/GP[30] G19
RMRXER/GP[52] A15
RMTXD1/GP[27]/
(LENDIAN)
H17
RMTXD0/GP[28]
H16
RMREFCLK/GP[31] D19
RMTXEN/GP[29] H15
ZDU
NO.
C4
A4
C6
A5
C5
B4
B5
A3
D3
B2
B6
D2
C3
B3
C2
K22
A19
L19
J21
G22
K21
TYPE ⁽¹⁾
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
OTHER ^{(2) (3)}
DESCRIPTION
EMAC (MII)
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Transmit Enable output MTXEN.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Transmit Clock input MTXCLK.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Collision Detect input MCOL.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Transmit Data 3 output MTXD3.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Transmit Data 2 output MTXD2.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Transmit Data 1 output MTXD1.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Transmit Data 0 output MTXD0.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Receive Clock input MRXCLK.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Receive Data Valid input
MRXDV.
IPD
DV_DD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Receive Error input MRXER.
IPD
DV_DD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Carrier Sense input MCRS.
IPU
DV_DD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Receive Data 3 input MRXD3.
IPU
DV_DD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Receive Data 2 input MRXD2.
IPU
DV_DD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Receive data 1 input MRXD1.
IPU
DV_DD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Receive Data 0 input MRXD0.
EMAC (RMII)
IPD
DV_DD33
This pin is multiplexed between EMAC (RMII) and GPIO.
In Ethernet MAC(RMII) mode, it is EMAC carrier sense/receive
data valid (RMCRSDV) [I].
IPD
DV_DD33
This pin is multiplexed between EMAC (RMII) and GPIO.
In Ethernet MAC(RMII) mode, it is EMAC receive error (RMRXER)
[I].
IPU
DV_DD33
This pin is multiplexed between EMAC (RMII) and GPIO.
In Ethernet MAC(RMII) mode, it is EMAC transmit data pin 1
(RMTXD1) [O/Z].
IPD
DV_DD33
This pin is multiplexed between EMAC (RMII) and GPIO.
In Ethernet MAC(RMII) mode, it is EMAC transmit data pin 0
(RMTXD0) [O/Z].
IPD
DV_DD33
This pin is multiplexed between EMAC (RMII) and GPIO.
In Ethernet MAC(RMII) mode, it is EMAC RMII reference clock
(RMREFCLK) [I].
IPD
DV_DD33
This pin is multiplexed between EMAC (RMII) and GPIO.
In Ethernet MAC(RMII) mode, it is EMAC transmit enable
(RMTXEN) [O/Z].
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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