TMS320C6421_17 Datasheet, PDF (208/222 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346D – JANUARY 2007 – REVISED JUNE 2008
6.19.2 VLYNQ Electrical Data/Timing
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Table 6-77. Timing Requirements for VLYNQ_CLK Input (see Figure 6-45)
NO.
1
t_c(VCLK)
2
t_w(VCLKH)
3
t_w(VCLKL)
Cycle time, VLYNQ_CLK
Pulse duration, VLYNQ_CLK high
Pulse duration, VLYNQ_CLK low
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
MIN
MAX
10
3
3
UNIT
ns
ns
ns
Table 6-78. Switching Characteristics Over Recommended Operating Conditions for VLYNQ_CLK Output
(see Figure 6-45)
NO.
PARAMETER
1 t_c(VCLK)
Cycle time, VLYNQ_CLK
2 t_w(VCLKH) Pulse duration, VLYNQ_CLK high
3 t_w(VCLKL) Pulse duration, VLYNQ_CLK low
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
MIN MAX
10
4
4
UNIT
ns
ns
ns
VLYNQ_CLK
1
2
3
Figure 6-45. VLYNQ_CLK Timing for VLYNQ
Table 6-79. Switching Characteristics Over Recommended Operating Conditions for Transmit Data for the
VLYNQ Module (see Figure 6-46)
NO.
PARAMETER
1 ^td(VCLKH-
TXDI)
2 ^td(VCLKH-
TXDV)
Delay time, VLYNQ_CLK high to VLYNQ_TXD[3:0] invalid
Delay time, VLYNQ_CLK high to VLYNQ_TXD[3:0] valid
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
MIN MAX
2.25
UNIT
ns
12 ns
208 Peripheral Information and Electrical Specifications
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