COP8CCE9_15 Datasheet, PDF (37/101 Pages) Texas Instruments – 8-Bit CMOS Flash Microcontroller with 8k Memory, Virtual EEPROM

COP8CCE9
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Command/
Label
uwisp
Function
MICROWIRE/
PLUS
ISP Start
SNOS978J – JUNE 2001 – REVISED MARCH 2013
Table 13. User ISP/Virtual E² Entry Points (continued)
Command
Entry Point
0x00
N/A
Parameters
Return Data
N/A (Device will be in MICROWIRE/PLUS
ISP Mode. Must be terminated by
MICROWIRE/PLUS ISP EXIT command
which will Reset the device)
Register
Name
ISPADHI
ISPADLO
ISPWR
ISPRD
ISPKEY
BYTECOUNTLO
PGMTIM
Confirmation Code
KEY
Table 14. Register and Bit Name Definitions
Purpose
High byte of Flash Memory Address
Low byte of Flash Memory Address
The user must store the byte to be written into this register before jumping into the write byte
routine.
Data will be returned to this register after the read byte routine execution.
The ISPKEY Register is required to validate the JSRB instruction and must be loaded within 6
instruction cycles before the JSRB.
Holds the count of the number of bytes to be read or written in block operations.
Write Timing Register. This register must be loaded, by the user, with the proper value before
execution of any USER ISP Write or Erase operation. Refer to Table 10 for the correct value.
The user must place this code in the accumulator before execution of a Flash Memory Mass Erase
command.
Must be transferred to the ISPKEY register before execution of a JSRB instruction.
RAM
Location
0xA9
0xA8
0xAB
0xAA
0xE2
0xF1
0xE1
A
0x98
RESTRICTIONS ON SOFTWARE WHEN CALLING ISP ROUTINES IN BOOT ROM
1. The hardware will disable interrupts from occurring. The hardware will leave the GIE bit in its current state,
and if set, the hardware interrupts will occur when execution is returned to Flash Memory. Subsequent
interrupts, during ISP operation, from the same interrupt source will be lost. Interrupts may occur between
setting the KEY and executing the JSRB instruction. In this case, the KEY will expire before the JSRB
is executed. It is, therefore, recommended that the software globally disable interrupts before setting
the Key.
2. The security feature in the MICROWIRE/PLUS ISP is ensured by software and not hardware. When
executing the MICROWIRE/PLUS ISP routine, the security bit is checked prior to performing all instructions.
Only the mass erase command, write PGMTIM register, and reading the Option register is permitted within
the MICROWIRE/PLUS ISP routine. When the user is performing his own ISP, all commands are permitted.
The entry points from the user's ISP code do not check for security. It is the burden of the user to ensure his
own security. See the Security bit description in OPTION REGISTER for more details on security.
3. When using any of the ISP functions in Boot ROM, the ISP routines will service the WATCHDOG within the
selected upper window. Upon return to flash memory, the WATCHDOG is serviced, the lower window is
enabled, and the user can service the WATCHDOG anytime following exit from Boot ROM, but must service
it within the selected upper window to avoid a WATCHDOG error.
4. Block Writes can start anywhere in the page of Flash memory, but cannot cross half page or full page
boundaries.
5. The user must ensure that a page erase or a mass erase is executed between two consecutive writes
to the same location in Flash memory. Two writes to the same location without an intervening erase
will produce unpredicatable results including possible disturbance of unassociated locations.
FLASH MEMORY DURABILITY CONSIDERATIONS
The endurance of the Flash Memory (number of possible Erase/Write cycles) is a function of the erase time and
the lowest temperature at which the erasure occurs. If the device is to be used at low temperature, additional
erase operations can be used to extend the erase time. The user can determine how many times to erase a
page based on what endurance is desired for the application (e.g. four page erase cycles, each time a page
erase is done, may be required to achieve the typical 100k Erase/Write cycles in an application which may be
operating down to 0°C). Also, the customer can verify that the entire page is erased, with software, and request
additional erase operations if desired.
Copyright © 2001–2013, Texas Instruments Incorporated
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