ADS8661 Datasheet, PDF (37/71 Pages) Texas Instruments – 12-Bit, High-Speed, Single-Supply, SAR ADC Data Acquisition System with Programmable, Bipolar Input Ranges

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ADS8661, ADS8665
SBAS780 – DECEMBER 2016
Device Functional Modes (continued)
7.4.2.1 RESET State
The device features an active-low RST pin that is an asynchronous digital input. In order to enter a RESET state,
the RST pin must be pulled low and kept low for the t_{wl_RST} duration (as specified in the Timing Requirements:
Asynchronous Reset table).
The device features two different types of reset functions: an application reset or a power-on reset (POR). The
functionality of the RST pin is determined by the state of the RSTn_APP bit in the RST_PWRCTL_REG register.
• In order to configure the RST pin to issue an application reset, the RSTn_APP bit in the RST_PWRCTL_REG
register must be configured to 1b. In this RESET state, all configuration registers (see the Register Maps
section) are reset to their default values, the RVS pins remain low, and the SDO-x pins are tri-stated.
• The default configuration for the RST pin is to issue a power-on reset when pulled to a low level. The
RSTn_APP bit is set to 0b in this state. When a POR is issued, all internal circuitry of the device (including
the PGA, ADC driver, and voltage reference) are reset. When the device comes out of the POR state, the
t_{D_RST_POR} time duration must be allowed for (see the Timing Requirements: Asynchronous Reset table) in
order for the internal circuitry to accurately settle.
In order to exit any of the RESET states, the RST pin must be pulled high with CONVST/CS and SCLK held low.
After a delay of t_{D_RST_POR} or t_{D_RST_APP} (see the Timing Requirements: Asynchronous Reset table), the device
enters ACQ state and the RVS pin goes high.
To operate the device in any of the other two states (ACQ or CONV), the RST pin must be held high. With the
RST pin held high, transitions on the CONVST/CS pin determine the functional state of the device. A typical
conversion cycle is illustrated in Figure 1.
7.4.2.2 ACQ State
In ACQ state, the device acquires the analog input signal. The device enters ACQ state on power-up, after any
asynchronous reset, or after the end of every conversion.
The falling edge of the RST falling edge takes the device from an ACQ state to a RESET state. A rising edge of
the CONVST/CS signal takes the device from ACQ state to a CONV state.
The device offers a low-power NAP mode to reduce power consumption in the ACQ state; see the NAP Mode
section for more details on NAP mode.
7.4.2.3 CONV State
The device moves from ACQ state to CONV state on the rising edge of the CONVST/CS signal. The conversion
process uses an internal clock and the device ignores any further transitions on the CONVST/CS signal until the
ongoing conversion is complete (that is, during the time interval of t_conv).
At the end of conversion, the device enters ACQ state. The cycle time for the device is given by Equation 1:
t_cycle-min t_conv t_acq-min
(1)
NOTE
The conversion time, t_conv, can vary within the specified limits of t_{conv_min} and t_{conv_max} (as
specified in the Timing Requirements: Conversion Cycle table). After initiating a
conversion, the host controller must monitor for a low-to-high transition on the RVS pin or
wait for the t_{conv_max} duration to elapse before initiating a new operation (data transfer or
conversion). If RVS is not monitored, substitute t_conv in Equation 1 with t_{conv_max}.
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