ADS8661 Datasheet, PDF (23/71 Pages) Texas Instruments – 12-Bit, High-Speed, Single-Supply, SAR ADC Data Acquisition System with Programmable, Bipolar Input Ranges

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ADS8661, ADS8665
SBAS780 – DECEMBER 2016
The results indicated in Table 1 are based on an assumption that the analog input pin is driven by a very low
impedance source (R_S is approximately 0 Ω). However, if the source driving the input has higher impedance, the
current flowing through the protection diodes reduces further, thereby increasing the OVP voltage range. Note
that higher source impedances result in gain errors and contribute to overall system noise performance.
Figure 48 shows the voltage versus current response of the internal overvoltage protection circuit when the
device is powered on. According to this current-to-voltage (I-V) response, the current flowing into the device input
pin is limited by the 1-MΩ (or 1.2 MΩ for appropriate input ranges) input impedance. However, for voltages
beyond ±20 V, the internal node voltages surpass the break-down voltage for internal transistors, thus setting the
limit for overvoltage protection on the input pin.
The same overvoltage protection circuit also provides protection to the device when the device is not powered on
and AVDD is floating with an impedance > 30 kΩ. This condition can arise when the input signals are applied
before the ADC is fully powered on. The overvoltage protection limits for this condition are shown in Table 2.
Table 2. Input Overvoltage Protection Limits When AVDD = Floating with Impedance > 30 kΩ⁽¹⁾
INPUT CONDITION
(V_OVP = ±11 V)
CONDITION
RANGE
|V_IN| < |V_OVP|
Within overvoltage range
|V_IN| > |V_OVP|
Beyond overvoltage range
TEST
CONDITION
All input ranges
All input ranges
ADC OUTPUT
COMMENTS
Invalid
Invalid
Device is not functional but is protected internally by the
OVP circuit.
This usage condition can cause irreversible damage to the
device.
(1) AVDD = floating, GND = 0 V, AIN_GND = 0 V, |V_RANGE| is the maximum input voltage for any selected input range, and |V_OVP| is the
break-down voltage for the internal OVP circuit. Assume that R_S is approximately 0 Ω.
Figure 49 shows the I-V response of the internal overvoltage protection circuit when the device is not powered
on. According to this I-V response, the current flowing into the device input pin is limited by the 1-MΩ input
impedance. However, for voltages beyond ±11 V, the internal node voltage surpasses the break-down voltage for
internal transistors, thus setting the limit for overvoltage protection on the input pin.
30
20
10
0
-10
-20
-30
-30 -24 -18 -12 -6 0 6 12 18 24 30
Input voltage (V)
D005
24
18
12
6
0
-6
-12
-18
-24
-20 -16 -12 -8 -4 0 4 8
Input voltage (V)
12 16 20
D006
Figure 48. I-V Curve for the Input OVP Circuit
(AVDD = 5 V)
Figure 49. I-V Curve for the Input OVP Circuit
(AVDD = Floating)
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