LM3S3Z26 Datasheet, PDF (368/877 Pages) Texas Instruments – Stellaris® LM3S3Z26 Microcontroller

Micro Direct Memory Access (μDMA)
Register 8: DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset
0x010
This read-only register indicates that the μDMA channel is waiting on a request. A peripheral can
hold off the μDMA from performing a single request until the peripheral is ready for a burst request
to enhance the μDMA performance. The use of this feature is dependent on the design of the
peripheral and is not controllable by software in any way. This register cannot be read when the
μDMA controller is in the reset state.
DMA Channel Wait-on-Request Status (DMAWAITSTAT)
Base 0x400F.F000
Offset 0x010
Type RO, reset 0xFFFF.FFC0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WAITREQ[n]
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WAITREQ[n]
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
Bit/Field
31:0
Name
WAITREQ[n]
Type
Reset Description
RO 0xFFFF.FFC0 Channel [n] Wait Status
These bits provide the channel wait-on-request status. Bit 0 corresponds
to channel 0.
Value Description
1 The corresponding channel is waiting on a request.
0 The corresponding channel is not waiting on a request.
368
January 21, 2012
Texas Instruments-Production Data