TMS320DM6467_17 Datasheet, PDF (36/355 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
SPRS403H – DECEMBER 2007 – REVISED JUNE 2012
www.ti.com
Table 3-9. Asynchronous External Memory Interface (EMIFA) Terminal Functions (continued)
SIGNAL
NAME
PCI_RSV4/DIOW/
GP[20]/EM_WAIT4/
(RDY4/BSY4)
PCI_RSV3/DIOR/
GP[19]/EM_WAIT5/
(RDY5/BSY5)
PCI_FRAME/
HINT/
EM_BA[0]
PCI_DEVSEL/
HCNTL1/
EM_BA[1]
PCI_RSV2/INTRQ/
GP[18]/EM_RSV0
PCI_RST/
DA2/
GP[13]/EM_A[22]
PCI_RSV0/DA1/
GP[16]/EM_A[21]
PCI_RSV1/DA0/
GP[17]/EM_A[20]
PCI_CBE1/
ATA_CS1/
GP[32]/EM_A[19]
PCI_CBE0/
ATA_CS0/
GP[33]/EM_A[18]
PCI_IRDY/
HRDY/
EM_A[17]/(CLE)
PCI_TRDY/
HHWIL/
EM_A[16]/(ALE)
PCI_AD31/
DD15/
HD31/EM_A[15]
PCI_AD30/
DD14/
HD30/EM_A[14]
PCI_AD29/
DD13/
HD29/EM_A[13]
PCI_AD28/
DD12/
HD28/EM_A[12]
PCI_AD27/
DD11/
HD27/EM_A[11]
PCI_AD26/
DD10/
HD26/EM_A[10]
TYPE ⁽¹⁾ OTHER^{(2) (3)}
NO.
DESCRIPTION
A11 I/O/Z
IPU
DV_DD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is wait state extension input 4 EM_WAIT4 (I).
When used for EMIFA (NAND), this pin is the ready/busy 4 input (RDY4/BSY4).
E10 I/O/Z
IPU
DV_DD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
For EMIFA, this pin is wait state extension input 5 EM_WAIT5 (I).
When used for EMIFA (NAND), this pin is the ready/busy 5 input (RDY5/BSY5).
D6 I/O/Z
IPU
DV_DD33
This pin is multiplexed between PCI, HPI, and EMIFA.
For EMIFA, this is the Bank Address 0 output EM_BA[0] (O/Z).
When connected to a 16-bit asynchronous memory, this pin has the same
function as EMIF address pin 22 (EM_A[22]).
When connected to an 8-bit asynchronous memory, this pin is the lowest order bit
of the byte address.
B3 I/O/Z
IPU
DV_DD33
This pin is multiplexed between PCI, HPI, and EMIFA.
For EMIFA, this is the Bank Address 1 output EM_BA[1] (O/Z).
When connected to a 16 bit asynchronous memory this pin is the lowest order bit
of the 16-bit word address.
When connected to an 8-bit asynchronous memory, this pin is the second bit of
the address.
B10 I/O/Z
IPD
DV_DD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is reserved.
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
C10 I/O/Z
IPD
DV_DD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is address bit 22 output EM_A[22] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
A9 I/O/Z
IPD
DV_DD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is address bit 21 output EM_A[21] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
E9 I/O/Z
IPD
DV_DD33
This pin is multiplexed between PCI ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is address bit 20 output EM_A[20] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
C2 I/O/Z
IPU
DV_DD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is address bit 19 output EM_A[19] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
F4 I/O/Z
IPU
DV_DD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is address bit 18 output EM_A[18] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
A3 I/O/Z
IPU
DV_DD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, this pin is address bit 17 output EM_A[17] (O/Z).
When used for EMIFA (NAND), this pin is Command Latch Enable output (CLE).
E6 I/O/Z
IPU
DV_DD33
This pin is multiplexed between PCI, HPI, and EMIFA.
For EMIFA, this pin is address bit 16 output EM_A[16] (O/Z).
When used for EMIFA (NAND), this pin is Address Latch Enable output (ALE).
A8 I/O/Z
IPD
DV_DD33
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 15 output EM_A[15] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
C9 I/O/Z
IPD
DV_DD33
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 14 output EM_A[14] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
B8 I/O/Z
IPD
DV_DD33
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 13 output EM_A[13] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
D9 I/O/Z
IPD
DV_DD33
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 12 output EM_A[12] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
A6 I/O/Z
IPD
DV_DD33
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 11 output EM_A[11] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
C8 I/O/Z
IPD
DV_DD33
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 10 output EM_A[10] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
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