DP83848C_15 Datasheet, PDF (36/86 Pages) Texas Instruments – Industrial Controls and Factory Automation

DP83848C, DP83848I
DP83848VYB, DP83848YB
SNLS266E – MAY 2007 – REVISED MARCH 2015
www.ti.com
Figure 6-2. Typical MDC/MDIO Read Operation
Figure 6-3. Typical MDC/MDIO Write Operation
6.4.3.3 Serial Management Preamble Suppression
The DP83848VYB supports a Preamble Suppression mode as indicated by a one in bit 6 of the Basic
Mode Status Register (BMSR, address 01h.) If the station management entity (for example, MAC or other
management controller) determines that all PHYs in the system support Preamble Suppression by
returning a one in this bit, then the station management entity need not generate preamble for each
management transaction.
The DP83848VYB requires a single initialization sequence of 32 bits of preamble following
hardware/software reset. This requirement is generally met by the mandatory pullup resistor on MDIO in
conjunction with a continuous MDC, or the management access made to determine whether Preamble
Suppression is supported.
While the DP83848VYB requires an initial preamble sequence of 32 bits for management initialization, it
does not require a full 32-bit sequence between each subsequent transaction. A minimum of one idle bit
between management transactions is required as specified in the IEEE 802.3 specification.
6.4.4 10 Mb Serial Network Interface (SNI)
The DP83848VYB incorporates a 10-Mb Serial Network Interface (SNI) which allows a simple serial data
interface for 10-Mb only devices. This is also referred to as a 7-wire interface. While there is no defined
standard for this interface, it is based on early 10-Mb physical layer devices. Data is clocked serially at 10
MHz using separate transmit and receive paths. The following pins are used in SNI mode:
• TX_CLK
• TX_EN
• TXD[0]
• RX_CLK
• RXD[0]
• CRS
• COL
6.4.5 PHY Address
The 5 PHY address inputs pins are shared with the RXD[3:0] pins and COL pin are shown in Table 6-5.
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Detailed Description
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