MSC1200_14 Datasheet, PDF (35/93 Pages) Texas Instruments – MSC1200 and MSC1201: 24 Bits No Missing Codes 22 Bits Effective Resolution At 10Hz

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REGISTER MAP
Figure 21 illustrates the Register Map. It is entirely
separate from the Program and Data Memory areas
discussed previously. A separate class of instructions is
used to access the registers. There are 256 potential
register locations. In practice, the MSC120x have 256
bytes of Scratchpad RAM and up to 128 SFRs. This is
possible since the upper 128 Scratchpad RAM locations
can only be accessed indirectly. Thus, a direct reference
to one of the upper 128 locations must be an SFR access.
Direct RAM is reached at locations 0 to 7Fh (0 to 127).
255
Indirect
RAM
128
127
Direct
RAM
0
Scratchpad
RAM
FFh 255
FFh
Direct
Special Function
80h 128
Registers
80h
7Fh
SFR Registers
00h
Figure 21. Register Map
SFRs are accessed directly between 80h and FFh (128 to
255). The RAM locations between 128 and 255 can be
reached through an indirect reference to those locations.
Scratchpad RAM is available for general-purpose data
storage. Within the 128 bytes of RAM, there are several
special-purpose areas.
Bit Addressable Locations
In addition to direct register access, some individual bits
are also accessible. These are individually addressable
bits in both the RAM and SFR area. In the Scratchpad
RAM area, registers 20h to 2Fh are bit-addressable. This
provides 128 (16 × 8) individual bits available to software.
A bit access is distinguished from a full-register access by
the type of instruction. In the SFR area, any register
location ending in a 0h or 8h is bit-addressable. Figure 22
shows details of the on-chip RAM addressing including the
locations of individual RAM bits.
Working Registers
As part of the lower 128 bytes of RAM, there are four banks
of Working Registers, as shown in Figure 20. The Working
Registers are general-purpose RAM locations that can be
addressed in a special way. They are designated R0
through R7. Since there are four banks, the currently
selected bank will be used by any instruction using R0−R7.
This design allows software to change context by simply
switching banks. Bank access is controlled via the
MSC1200
MSC1201
MSC1202
SBAS317E − APRIL 2004 − REVISED MAY 2006
Program Status Word register (PSW; 0D0h) in the SFR
area described below. The 16 bytes immediately above
the R0−R7 registers are bit-addressable, so any of the 128
bits in this area can be directly accessed using
bit-addressable instructions.
7Fh
Direct
RAM
2Fh 7F 7E 7D 7C 7B 7A 79 78
2Eh 77 76 75 74 73 72 71 70
2Dh 6F 6E 6D 6C 6B 6A 69 68
2Ch 67 66 65 64 63 62 61 60
2Bh 5F 5E 5D 5C 5B 5A 59 58
2Ah 57 56 55 54 53 52 51 50
29h 4F 4E 4D 4C 4B 4A 49 48
28h 47 46 45 44 43 42 41 40
27h 3F 3E 3D 3C 3B 3A 39 38
26h 37 36 35 34 33 32 31 30
25h 2F 2E 2D 2C 2B 2A 29 28
24h 27 26 25 24 23 22 21 20
23h ^{1F 1E 1D 1C 1B 1A 19 18}
22h ^{17 16 15 14 13 12 11 10}
21h ^{0F 0E 0D 0C 0B 0A 09 08}
20h 07 06 05 04 03 02 01 00
1Fh
Bank 3
18h
17h
Bank 2
10h
0Fh
Bank 1
08h
07h
Bank 0
00h
MSB
LSB
Figure 22. Scratchpad Register Addressing
Thus, an instruction can designate the value stored in R0
(for example) to address the upper RAM. The 16 bytes
immediately above the these registers are
bit-addressable, so any of the 128 bits in this area can be
directly accessed using bit-addressable instructions.
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