MSC1200_14 Datasheet, PDF (20/93 Pages) Texas Instruments – MSC1200 and MSC1201: 24 Bits No Missing Codes 22 Bits Effective Resolution At 10Hz

MSC1200
MSC1201
MSC1202
SBAS317E − APRIL 2004 − REVISED MAY 2006
ENHANCED 8051 CORE
All instructions in the MSC120x families perform exactly
the same functions as they would in a standard 8051. The
effects on bits, flags, and registers are the same; however,
the timing is different. The MSC120x families use an
efficient 8051 core that results in an improved instruction
execution speed of between 1.5 and 3 times faster than the
original core for the same external clock speed (4 clock
cycles per instruction versus 12 clock cycles per
instruction, as shown in Figure 4). This efficiency
translates into an effective throughput improvement of
more than 2.5 times, using the same code and same
external clock speed. Therefore, a device frequency of
33MHz for the MSC120x actually performs at an
equivalent execution speed of 82.5MHz compared to the
standard 8051 core. This increased performance allows
the device to be tun at slower clock speeds, which reduces
system noise and power consumption, but provides
greater throughput. This performance difference can be
seen in Figure 5. The timing of software loops will be faster
with the MSC120x. However, the timer/counter operation
of the MSC120x may be maintained at 12 clocks per
increment or optionally run at 4 clocks per increment.
The MSC120x also provide dual data pointers (DPTRs).
www.ti.com
Single−Byte, Single−Cycle
Instruction
Internal
ALE
Internal
PSEN
Internal
AD0−AD7
Internal
A8−A15
4 Cycles
CLK
ALE
PSEN
AD0−AD7
PORT 2
12 Cycles
Single−Byte, Single−Cycle
Instruction
Figure 5. Comparison of MSC120x Timing to
Standard 8051 Timing
f_CLK
instr_cycle
n+1
n+2
cpu_cycle
C1
C2
C3
C4
C1
C2
C3
C4
C1
Figure 4. Instruction Timing Cycle
20