FDC2212_16 Datasheet, PDF (35/61 Pages) Texas Instruments – EMI-Resistant 28-Bit,12-Bit Capacitance-to-Digital Converter

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FDC2212, FDC2214, FDC2112, FDC2114
SNOSCZ5A – JUNE 2015 – REVISED JUNE 2015
Bit
14:13
12:3
2:0
Table 39. Address 0x1B, MUX_CONFIG Field Descriptions (continued)
Field
RR_SEQUENCE
RESERVED
DEGLITCH
Type
R/W
R/W
R/W
Reset
00
00 0100
0001
111
Description
Auto-Scan Sequence Configuration Configure multiplexing
channel sequence. The FDC will perform a single conversion on
each channel in the sequence selected, and then restart the
sequence continuously.
b00: Ch0, Ch1
b01: Ch0, Ch1, Ch2 (FDC2114, FDC2214 only)
b10: Ch0, Ch1, Ch2, Ch3 (FDC2114, FDC2214 only)
b11: Ch0, Ch1
Reserved. Must be set to 00 0100 0001
Input deglitch filter bandwidth.
Select the lowest setting that exceeds the oscillation tank
oscillation frequency.
b001: 1MHz
b100: 3.3MHz
b101: 10MHz
b111: 33MHz
9.6.30 Address 0x1C, RESET_DEV
15
14
RESET_DEV
7
6
Figure 47. Address 0x1C, RESET_DEV
13
12
11
10
9
RESERVED
OUTPUT_GAIN
5
4
3
2
1
RESERVED
8
RESERVED
0
Bit
15
14:11
10:9
8:0
Field
RESET_DEV
RESERVED
OUTPUT_GAIN
RESERVED
Table 40. Address 0x1C, RESET_DEV Field Descriptions
Type
R/W
R/W
R/W
R/W
Reset
0
0000
00
0 0000
0000
Description
Device Reset
Write b1 to reset the device. Will always readback 0.
Reserved. Set to b0000
Output gain control (FDC2112, FDC2114 only)
00: Gain =1 (0 bits shift)
01: Gain = 4 (2 bits shift)
10: Gain = 8 (3 bits shift)
11: Gain = 16 (4 bits shift)
Reserved, Set to b0 0000 0000
9.6.31 Address 0x1E, DRIVE_CURRENT_CH0
Figure 48. Address 0x1E, DRIVE_CURRENT_CH0
15
14
13
12
11
10
9
8
CH0_IDRIVE
RESERVED
7
6
5
4
3
2
1
0
RESERVED
Copyright © 2015, Texas Instruments Incorporated
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