DP83849IF_14 Datasheet, PDF (35/104 Pages) Texas Instruments – PHYTER™ DUAL Industrial Temperature with Fiber Support (FX) and Flexible Port Switching Dual Port 10/100 Mb/s Ethernet Physical Layer Tranceiver

DP83849IF
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SNOSAX8C – JUNE 2008 – REVISED APRIL 2009
4.3 AUTO-MDIX
When enabled, this function utilizes Auto-Negotiation to determine the proper configuration for
transmission and reception of data and subsequently selects the appropriate MDI pair for MDI/MDIX
operation. The function uses a random seed to control switching of the crossover circuitry. This
implementation complies with the corresponding IEEE 802.3 Auto-Negotiation and Crossover
Specifications.
Auto-MDIX is enabled by default and can be configured via strap or via PHYCR (19h) register, bits [15:14].
Neither Auto-Negotiation nor Auto-MDIX is required to be enabled in forcing crossover of the MDI pairs.
Forced crossover can be achieved through the FORCE_MDIX bit, bit 14 of PHYCR (19h) register.
NOTE
Auto-MDIX will not work in a forced mode of operation.
4.4 PHY ADDRESS
The 4 PHY address inputs pins are shown below.
Pin #
4
5
58
57
Table 4-2. PHY Address Mapping
PHYAD Function
PHYAD1
PHYAD2
PHYAD3
PHYAD4
RXD Function
RXD0_A
RXD1_A
RXD0_B
RXD1_B
The DP83849IF provides four address strap pins for determining the PHY addresses for ports A and B of
the device. The 4 address strap pins provide the upper four bits of the PHY address. The lowest bit of the
PHY address is dependent on the port. Port A has a value of 0 for the PHY address bit 0 while port B has
a value of 1. The PHY address strap input pins are shown in Table 4-2.
The PHY address strap information is latched into the PHYCR register (address 19h, bits [4:0]) at device
power-up and hardware reset. The PHY Address pins are shared with the RXD pins. Each DP83849IF or
port sharing an MDIO bus in a system must have a unique physical address.
The DP83849IF supports PHY Address strapping of Port A to even values 0 (<0000_0>) through 30
(<1111_0>). Port B is strapped to odd values 1 (<0000_1>) through 31 (<1111_1>). Note that Port B
address is always 1 greater than Port A address.
For further detail relating to the latch-in timing requirements of the PHY Address pins, as well as the other
hardware configuration pins, refer to the Reset summary in Section 8.
Refer to Figure 4-1 for an example of a PHYAD connection to external components. In this example, the
PHYAD strapping results in address 00010 (02h) for Port A and address 00011 (03h) for Port B.
4.4.1 MII Isolate Mode
The DP83849IF can be put into MII Isolate mode by writing to bit 10 of the BMCR register.
When in the MII isolate mode, the DP83849IF does not respond to packet data present at TXD[3:0],
TX_EN inputs and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0],
COL, and CRS outputs. When in Isolate mode, the DP83849IF will continue to respond to all management
transactions.
While in Isolate mode, the PMD output pair will not transmit packet data but will continue to source
100BASE-TX scrambled idles or 10BASE-T normal link pulses.
Copyright © 2008–2009, Texas Instruments Incorporated
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