ADS6122 Datasheet, PDF (35/67 Pages) Texas Instruments – 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

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ADS6125, ADS6124
ADS6123, ADS6122
SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6122 (F_S= 65 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 V_PP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
SFDR vs INPUT FREQUENCY (LVDS interface)
100
96
92
88
Gain = 3.5 dB
84
80
76
Gain = 0 dB
72
68
64
60
0 50 100 150 200 250 300 350 400 450 500
f_IN − Input Frequency − MHz
G061
Figure 67.
SFDR vs INPUT FREQUENCY ACROSS GAINS
95
Input adjusted to get −1dBFS input
90
3 dB
85
80
1 dB
0 dB
75
2 dB
70
6 dB
5 dB
65
4 dB
60
0
100
200
300
400
f_IN − Input Frequency − MHz
Figure 69.
500
G063
PERFORMANCE vs AVDD
96
f_IN = 70.1 MHz
94 _{DRVDD = 3.3 V}
92
SFDR
90
88
86
SNR
84
82
80
3.0
3.1
3.2
3.3
3.4
3.5
AV_DD − Supply Voltage − V
Figure 71.
77
76
75
74
73
72
71
70
69
3.6
G065
SNR vs INPUT FREQUENCY (LVDS interface)
76
74
72
Gain = 0 dB
70
68
Gain = 3.5 dB
66
64
62
0
50 100 150 200 250 300 350 400 450 500
f_IN − Input Frequency − MHz
G062
Figure 68.
SINAD vs INPUT FREQUENCY ACROSS GAINS
76
Input adjusted to get −1dBFS input
74
72
0 dB 2 dB
1 dB
70
68
66
3 dB
64
4 dB ^{5 dB 6 dB}
62
60
0
100
200
300
400
f_IN − Input Frequency − MHz
Figure 70.
500
G064
PERFORMANCE vs DRVDD
106
75
f_IN = 10.1 MHz
104 AV_DD = 3.3 V
74
102
73
SNR
100
72
98
71
SFDR
96
70
94
69
92
68
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
DRV_DD − Supply Voltage − V
G066
Figure 72.
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