ADS6122 Datasheet, PDF (1/67 Pages) Texas Instruments – 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

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ADS6125, ADS6124
ADS6123, ADS6122
SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
FEATURES
1
• Maximum Sample Rate: 125 MSPS
• 12-Bit Resolution with No Missing Codes
• 3.5 dB Coarse Gain and up to 6 dB
Programmable Fine Gain for SNR/SFDR
Trade-Off
• Parallel CMOS and Double Data Rate (DDR)
LVDS Output Options
• Supports Sine, LVCMOS, LVPECL, LVDS Clock
Inputs and Clock Amplitude Down to 400 mV_PP
• Clock Duty Cycle Stabilizer
• Internal Reference with Support for External
Reference
• No External Decoupling Required for
References
• Programmable Output Clock Position and
Drive Strength to Ease Data Capture
• 3.3 V Analog and 1.8 V to 3.3 V Digital Supply
• 32-QFN Package (5 mm × 5 mm)
• Pin Compatible 12-Bit Family (ADS612X)
APPLICATIONS
• Wireless Communications Infrastructure
• Software Defined Radio
• Power Amplifier Linearization
• 802.16d/e
• Test and Measurement Instrumentation
• High Definition Video
• Medical Imaging
• Radar Systems
DESCRIPTION
ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X)
is a family of 12-bit A/D converters with sampling
frequencies up to 125 MSPS. It combines high
performance and low power consumption in a
compact 32 QFN package. Using an internal high
bandwidth sample and hold and a low jitter clock
buffer helps to achieve high SNR and high SFDR
even at high input frequencies.
It features coarse and fine gain options that are used
to improve SFDR performance at lower full-scale
analog input ranges.
The digital data outputs are either parallel CMOS or
DDR LVDS (Double Data Rate). Several features
exist to ease data capture such as — controls for
output clock position and output buffer drive strength,
and LVDS current and internal termination
programmability.
The output interface type, gain, and other functions
are programmed using a 3-wire serial interface.
Alternatively, some of these functions are configured
using dedicated parallel pins so that the device
comes up in the desired state after power-up.
ADS612X includes internal references, while
eliminating the traditional reference pins and
associated external decoupling. External reference
mode is also supported.
The devices are specified over the industrial
temperature range (–40°C to 85°C).
ADS612X Performance Summary
SFDR, dBc
SINAD, dBFS
F_in = 10 MHz (0 dB gain)
F_in = 170 MHz (3.5 dB gain)
F_in = 10 MHz (0 dB gain)
F_in = 170 MHz (3.5 dB gain)
Power, mW
ADS6125
90
78
71.1
67.6
417
ADS6124
91
82
71.3
69.1
374
ADS6123
93
83
71.5
69.2
318
ADS6122
95
84
71.6
69.8
285
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated