UCC28251 Datasheet, PDF(34/54 Page) Texas Instruments – Advanced PWM Controller With Pre-Bias Operation

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UCC28251 Datasheet, PDF (34/54 Pages) Texas Instruments – Advanced PWM Controller With Pre-Bias Operation

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UCC28251

SLUSBD8D â FEBRUARY 2013 â REVISED APRIL 2013

www.ti.com

Pre-Biased Start Up

With the internal error amplifier, UCC28251 supports both primary-side control and secondary-side control. For

different control methods, the controller is configured accordingly and so is the pre-biased start-up control. During

soft start, both the primary-side switchesâ duty cycle and secondary-side SRsâ duty cycle are increased. This

gradually increases the output voltage until steady state operation is reached, thereby reducing surge current.

Secondary-Side Control

For secondary-side control, the UCC28251 implements close-loop control of both the primary-side switches and

secondary-side synchronous rectifiersâ duty cycles. This makes it easy to achieve optimal start up performance.

The internal error amplifier is set up as the control loop error amplifier. Connect REF/EA+, FB/EA-, COMP and

VSENSE as shown in Figure 41. To achieve optimal pre-biased start up performance, the output voltage needs

to be directly measured. The UCC28251 uses the VSENSE pin to directly sense this output voltage. Choose the

voltage dividers on VSENSE slightly different to the FB/EA- voltage divider so that the voltage on VSENSE pin is

roughly 10% to 15% more than FB/EA- pin voltages. Select RO1 equal to RS1, and RS2 about 10% to 15% smaller

than RO2.

VOUT

RO2

RZ3

RS2

CP1

RZ2

CZ2

UCC28251

VSENSE

VREF

COMP

CZ3

FB/EA-

RS1

RO1

REF /EA +

CSS

Figure 41. Error Amplifier Set Up for Secondary-Side Control

The error amplifier uses the lower voltage between the SS pin and the REF/EA+ pin to be the reference voltage

for the feedback loop. In this method, the control loop is said to be âclosedâ during the entire start up process, as

it is always based on the true output voltage.

During soft start, the primary-side switch duty cycle is controlled by the COMP pin voltage and ramp voltage

generated on the RAMP/CS pin. A higher COMP pin voltage results in larger duty cycle. However, to improve

start up performance, the secondary-side synchronous rectifier duty cycle is controlled by a separate, internal

ramp signal (generated by a dedicated pre-biased start up loop) and by the COMP pin voltage. This dedicated

pre-biased loop is much faster than the regular voltage loop in order to avoid interaction between the two loops.

The start up loop reads the output voltage via a transconductance error amplifier connected to the VSENSE pin.

When the output voltage is higher than the reference, the pre-biased start up loop increases the SR duty cycle to

reduce the output voltage. Conversely, when the output voltage is lower than the reference, the SR duty cycle is

decreased to help maintain higher output voltage. To speed up the start up time, the minimum duty cycle of the

synchronous rectifier is 50%.

Once the soft start is finished, the pre-biased loop is disabled and the duty cycle of the synchronous rectifiers

becomes the complimentary of primary switchesâ duty cycle, with some dead time inserted in between.

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