ADS9110 Datasheet, PDF (34/62 Pages) Texas Instruments – 18-Bit, 2-MSPS, 15-mW, SAR ADC

ADS9110
SBAS629A – OCTOBER 2015 – REVISED OCTOBER 2015
www.ti.com
Figure 57, Figure 58, Figure 59, and Figure 60 explain the details of the four protocols using an optimal, 20-
SCLK frame. As explained in the Data Transfer Frame section, the host controller can use a short data transfer
frame to read only the required number of MSB bits from the 20-bit output data word.
With SDO_CNTL[7:0] = 00h, if the host controller uses a long data transfer frame, the device exhibits daisy-chain
operation (see the Multiple Devices: Daisy-Chain Topology section).
CS
SCLK
SDO-0
D19
D18
D17
D19 D18
D17
D19
D18
D1
D0
D1
D0
D1
D0
CS
SCLK
SDO-0
D19
D18
D1
D0
D19
D18
D17
0 D19 D18
D0
D1 D0
RVS
RVS
CS
SCLK
SDO-0
Figure 57. SPI-00-S Protocol, 20 SCLKs
D19
D19
D18
D17
D1
D0
D18
D17
D19
D18
D1
D0
D1
D0
CS
SCLK
SDO-0
Figure 58. SPI-01-S Protocol, 20 SCLKs
D19 D18
D17
D1
D0
D19 D18
0 D19 D18
D2
D1
D0
D2
D1 D0
RVS
RVS
Figure 59. SPI-10-S Protocol, 20 SCLKs
Figure 60. SPI-11-S Protocol, 20 SCLKs
7.5.3.2.2 SPI-Compatible Protocols with Bus Width Options
The device provides an option to increase the SDO bus width from one bit (default, single SDO) to two bits (dual
SDO) or to four bits (quad SDO) when operating with any of the four legacy, SPI-compatible protocols.
Set the SDO_WIDTH[1:0] bits in the SDO_CNTL register to select the SDO bus width.
In dual SDO mode (SDO_WIDTH[1:0] = 10b), two bits of data are launched on the two SDO pins (SDO-0 and
SDO-1) on every SCLK launch edge.
In quad SDO mode (SDO_WIDTH[1:0] = 11b), four bits of data are launched on the four SDO pins (SDO-0,
SDO-1, SDO-2, and SDO-3) on every SCLK launch edge.
The SCLK launch edge depends upon the SPI protocol selection (as shown in Table 6).
PROTOCOL
SPI-00-D
SPI-01-D
SPI-10-D
SPI-11-D
SPI-00-Q
SPI-01-Q
SPI-10-Q
SPI-11-Q
Table 6. SPI-Compatible Protocols with Bus Width Options
SCLK POLARITY
(At CS Falling
Edge)
Low
Low
High
High
Low
Low
High
High
SCLK PHASE
(Capture Edge)
Rising
Falling
Falling
Rising
Rising
Falling
Falling
Rising
MSB BIT
LAUNCH EDGE
CS falling
First SCLK rising
CS falling
First SCLK falling
CS falling
First SCLK rising
CS falling
First SCLK falling
SDI_CNTL
00h
01h
02h
03h
00h
01h
02h
03h
SDO_CNTL
08h
08h
08h
08h
0Ch
0Ch
0Ch
0Ch
DIAGRAM
Figure 61
Figure 62
Figure 63
Figure 64
Figure 65
Figure 66
Figure 67
Figure 68
34
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