ADS9110 Datasheet, PDF (31/62 Pages) Texas Instruments – 18-Bit, 2-MSPS, 15-mW, SAR ADC

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ADS9110
SBAS629A – OCTOBER 2015 – REVISED OCTOBER 2015
7.5.3 Data Transfer Protocols
The device features a multiSPI interface that allows the host controller to operate at slower SCLK speeds and
still achieve the required cycle time with a faster response time. The multiSPI interface module offers two options
to reduce the SCLK speed required for data transfer:
1. An option to increase the width of the output data bus
2. An option to enable double data rate (DDR) transfer
These two options can be combined to achieve further reduction in SCLK speed.
Figure 51 shows the delays between the host controller and the device in a typical serial communication.
Device
SCLK
Digital Isolator
(Optional)
t_{pcb_CK}
Host Controller
SCLK
t_{d_ckdo}
SDO-0
t_{d_ISO}
t_{d_ISO}
t_{pcb_SDO}
t_{su_h}
SDI
Figure 51. Delays in Serial Communication
The total delay in the path is given by Equation 11:
t_{d_total_serial} t_{pcb_CK} t_{d_iso} t_{d_ckdo} t_{d_iso} t_{pcb_SDO} t_{su_h}
(11)
In a standard SPI protocol, the host controller and the device launch and capture data bits on alternate SCLK
edges. Therefore, the t_{d_total_serial} delay must be kept less than half of the SCLK duration. Equation 12 shows the
fastest clock allowed by the SPI protocol.
f_clk-SPI
d
1
2 u t_{d_total-serial}
(12)
Larger values of the t_{d_total_serial} delay restrict the maximum SCLK speed for the SPI protocol, resulting in higher
read and response times, and can increase cycle times. To remove this restriction on the SCLK speed, the
multiSPI interface module supports an ADC-master or source-synchronous mode of operation.
Device
SCLK
Digital Isolator
(Optional)
t_{pcb_CK}
Host Controller
SCLK
t_{d_ckdo}
t_{d_ckstr}
SDO-0
t_{off_strdo}
t_{d_ISO}
t_{d_ISO}
t_{pcb_SDO}
SDI
t_{su_h}
RVS
t_{d_ISO}
t_{pcb_RVS}
Figure 52. Delays in Source-Synchronous Communication
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