MSC1211_16 Datasheet, PDF (33/109 Pages) Texas Instruments – Percision Analog-to-Digital Converter and Digital-to-Analog Converters

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MEMORY MAP
The MSC1211/12/13/14 contain on-chip SFR, Flash
Memory, Scratchpad SRAM Memory, Boot ROM, and
SRAM. The SFR registers are primarily used for control
and status. The standard 8051 features and additional
peripheral features of the MSC1211/12/13/14 are
controlled through the SFR. Reading from an undefined
SFR will return zero; writing to an undefined SFR is not
recommended, and will have indeterminate effects.
Flash Memory is used for both Program Memory and Data
Memory. The user has the ability to select the partition size
of Program and Data Memory. The partition size is set
through hardware configuration bits, which are
programmed through either the parallel or serial
programming methods. Both Program and Data Flash
Memory are erasable and writable (programmable) in User
Application mode (UAM). However, program execution
can only occur from Program Memory. As an added
precaution, a lock feature can be activated through the
hardware configuration bits, which disables erase and
writes to 4kB of Program Flash Memory or the entire
Program Flash Memory in UAM.
The MSC1211/12/13/14 include 1kB of SRAM on-chip.
SRAM starts at address 0 and is accessed through the
MOVX instruction. This SRAM can also be located to start
at 8400h and can be accessed as both Program and Data
Memory.
MSC1211, MSC1212
MSC1213, MSC1214
SBAS323G − JUNE 2004 − REVISED OCTOBER 2007
FLASH MEMORY
The page size for Flash memory is 128 bytes. The
respective page must be erased before it can be written to,
regardless of whether it is mapped to Program or Data
Memory space. The MSC1211/12/13/14 use a memory
addressing scheme that separates Program Memory
(FLASH/ROM) from Data Memory (FLASH/RAM). Each
area is 64kB beginning at address 0000h and ending at
FFFFh, as shown in Figure 20. The program and data
segments can overlap since they are accessed in different
ways. Program Memory is fetched by the microcontroller
automatically. There is one instruction (MOVC) that is
used to explicitly read the program area. This instruction
is commonly used to read lookup tables. The Data Memory
area is accessed explicitly using the MOVX instruction.
This instruction provides multiple ways of specifying the
target address. It is also used to access the 64kB of Data
Memory. The address and data range of devices with
on-chip Program and Data Memory overlap the 64kB
memory space. When on-chip memory is enabled,
accessing memory in the on-chip range will cause the
device to access internal memory. Memory accesses
beyond the internal range will be addressed externally via
Ports 0 and 2.
The MSC1211/12/13/14 have two hardware configuration
registers (HCR0 and HCR1) that are programmable only
during Flash Memory Programming mode.
Program
Memory
FFFFh
2k Internal Boot ROM
F800h
External
Program
Memory
Mapped to Both
Memory Spaces
(von Neumann)
1k RAM or External
External Memory
8800h
8400h
7FFFh, 32k (Y5)
On−Chip
Flash
3FFFh, 16k (Y4)
1FFFh, 8k (Y3)
0FFFh, 4k (Y2)
0000h, 0k
Data
Memory
FFFFh
External
Data
Memory
1k RAM or External
8800h
83FFh, 33k (Y5)
On−Chip
Flash
43FFh, 17k (Y4)
23FFh, 9k (Y3)
13FFh, 5k (Y2)
03FFh, 1k
1k RAM or External
Configuration
Memory
Flash
Programming
Mode
Address
User
Application
Mode
Address⁽¹⁾
807Fh
7Fh
UAM: Read Only
FPM: Read/Write
8079h
79h
UAM: Read Only
FPM: Read Only
8070h
70h
UAM: Read Only
FPM: Read/Write
8000h
00h
NOTE: (1) Can be accessed using CADDR
or the faddr_data_read Boot ROM routine.
Figure 20. Memory Map
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