ADS62P24_14 Datasheet, PDF (33/78 Pages) Texas Instruments – DUAL CHANNEL, 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

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ADS62P24, ADS62P25
ADS62P22, ADS62P23
SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011
TYPICAL CHARACTERISTICS - ADS62P24 (F_S= 105 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 V_PP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
SFDR vs INPUT FREQUENCY (LVDS interface)
96
94
92
Gain = 3.5 dB
SFDR vs INPUT FREQUENCY ACROSS GAIN
96
Input adjusted to get −1dBFS input
94
92
5 dB
2 dB
3 dB
90
90
88
88
86
86
84
82
80
78
0
Gain = 0 dB
25 50 75 100 125 150 175 200
84
82
80
78
0
6 dB
25
0 dB
50 75
1 dB
4 dB
100 125 150 175 200
f_IN − Input Frequency − MHz
G025
Figure 31.
f_IN − Input Frequency − MHz
G027
Figure 32.
SINAD vs INPUT FREQUENCY ACROSS GAIN
73
Input adjusted to get −1dBFS input
72
0 dB
71
1 dB
2 dB
3 dB
70
69
68
67
66 ^{4 dB} 5 dB
6 dB
65
0
25 50 75 100 125 150 175 200
f_IN − Input Frequency − MHz
G028
Figure 33.
PERFORMANCE vs AVDD
88
f_IN = 70.1 MHz
87 _{DRVDD = 3.31 V}
86
SFDR
85
84
SNR
83
82
81
80
3.0
3.1
3.2
3.3
3.4
3.5
AV_DD − Supply Voltage − V
Figure 34.
76
75
74
73
72
71
70
69
68
3.6
G029
PERFORMANCE vs DRVDD
90
f_IN = 70.1 MHz
89 _{AVDD = 3.31 V}
88
87
SFDR
86
85
SNR
84
83
82
3.0
3.1
3.2
3.3
3.4
3.5
DRV_DD − Supply Voltage − V
Figure 35.
77
76
75
74
73
72
71
70
69
3.6
G030
PERFORMANCE vs TEMPERATURE
89
75
88
74
87
73
SFDR
86
72
SNR
85
71
84
f_IN = 70.1 MHz
83
−40 −20
0
20
40
60
T − Temperature − °C
Figure 36.
70
69
80
G031
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