ADS62P24_14 Datasheet, PDF (14/78 Pages) Texas Instruments – DUAL CHANNEL, 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

ADS62P24, ADS62P25
ADS62P22, ADS62P23
SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011
www.ti.com
DETAILS OF PARALLEL CONFIGURATION ONLY
The functions controlled by each parallel pin are described below. A simple way of configuring the parallel pins is
shown in Figure 5.
SCLK
0
(3/8)AVDD
(5/8)2AVDD
AVDD
Table 4. SCLK (Analog Control Pin)
DESCRIPTION
0dB gain and internal reference
0dB gain and external reference
3.5dB coarse gain and external reference
3.5dB coarse gain and internal reference
SEN
0
(3/8)AVDD
(5/8)AVDD
AVDD
Table 5. SEN (Analog Control Pin)
DESCRIPTION
2s complement format and DDR LVDS output
Straight binary and DDR LVDS output
Straight binary and parallel CMOS output
2s complement format and parallel CMOS output
CTRL1
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
CTRL2
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
Table 6. CTRL1, CTRL2 and CTRL3 (Digital Control Pins)
CTRL3
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
DESCRIPTION
Normal operation
Channel A output buffer disabled
Channel B output buffer disabled
Channel A and B output buffer disabled
Channel A and B powered down
Channel A standby
Channel B standby
MUX mode of operation (only with CMOS interface Channel A and B data is multiplexed and
output on DB11 to DB0 pins
. See multiplexed output mode for detailed description.
AVDD
3R
(5/8) AVDD
(5/8) AVDD
2R
(3/8) AVDD
GND
AVDD
3R
(3/8) AVDD
To Parallel Pin
GND
S0321-01
Figure 5. Simple Scheme to Configure Parallel Pins
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