66AK2H14 Datasheet, PDF (322/351 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

66AK2H14/12/06
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS866E—November 2013
Table 10-45 UART Switching Characteristics
(See Figure 10-44 and Figure 10-45)
No.
Parameter
Transmit Timing
1 tw(TXSTART)
Pulse width, transmit start bit
2 tw(TXH)
Pulse width, transmit data/parity bit high
2 tw(TXL)
Pulse width, transmit data/parity bit low
3 tw(TXSTOP1)
Pulse width, transmit stop bit 1
3 tw(TXSTOP15)
Pulse width, transmit stop bit 1.5
3 tw(TXSTOP2)
Pulse width, transmit stop bit 2
Autoflow Timing Requirements
7 td(RX-RTSH)
End of Table 10-45
Delay time, STOP bit received to RTS deasserted
1 U = UART baud time = 1/programmed baud rate
2 P = 1/(SYSCLK1/6)
Figure 10-44 UART Transmit Timing Waveform
1
2
TXD
Stop/Idle
Start
Bit 0
Bit 1
Bit N-1 Bit N
2
Parity
Figure 10-45 UART RTS (Request-to-Send Output) – Autoflow Timing Waveform
7
RXD
Bit N-1 Bit N
Stop
Min
Max
Unit
U ⁽¹⁾- 2
U + 2 ns
U-2
U + 2 ns
U-2
U + 2 ns
U-2
U + 2 ns
1.5 * (U - 2) 1.5 * ('U + 2) ns
2 * (U - 2) 2 * ('U + 2) ns
P ⁽²⁾
5P ns
3
Stop
Idle
Start
Start
CTS
10.14 PCIe Peripheral
The two-lane PCI express (PCIe) module on 66AK2H14/12/06 provides an interface between the device and other
PCIe-compliant devices. The PCIe module provides low pin-count, high-reliability, and high-speed data transfer at
rates up to 5.0 Gbps per lane on the serial links. For more information, see the Peripheral Component Interconnect
Express (PCIe) for KeyStone Devices User Guide in .
10.15 Packet Accelerator
The Packet Accelerator (PA) provides L2 to L4 classification functionalities and supports classification for Ethernet,
VLAN, MPLS over Ethernet, IPv4/6, GRE over IP, and other session identification over IP such as UDP ports. It
maintains 8k multiple-in, multiple-out hardware queues and also provides checksum capability as well as some QoS
capabilities. The PA enables a single IP address to be used for a multicore device and can process up to 1.5 Mpps.
The Packet Accelerator is coupled with the Network Coprocessor. For more information, see the Packet Accelerator
(PA) for KeyStone Devices User Guide in 2.6 ‘‘Related Documentation from Texas Instruments’’ on page 19.
322 66AK2H14/12/06 Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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