LM12454_14 Datasheet, PDF (32/45 Pages) Texas Instruments – LM12454/LM12458/LM12H458 12-Bit + Sign Data Acquisition System with Self-Calibration

LM12454, LM12458, LM12H458
SNAS079A – MAY 2004 – REVISED FEBRUARY 2006
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Bit 10 activates the Test mode that is used only during production testing. Leave this bit reset to “0”.
Bit 11 is the Diagnostic bit and is available only in the LM12(H)458. It can be activated by setting it to a “1” (the
Test bit must be reset to a “0”). The Diagnostic mode, along with a correctly chosen instruction, allows
verification that the LM12(H)458's ADC is performing correctly. When activated, the inverting and non-inverting
inputs are connected as shown in Table 6. As an example, an instruction with “001” for both V_IN+ and V_IN− while
using the Diagnostic mode typically results in a full-scale output.
2.3 INTERRUPTS
The LM12454 and LM12(H)458 have eight possible interrupts, all with the same priority. Any of these interrupts
will cause a hardware interrupt to appear on the INT pin (31) if they are not masked (by the Interrupt Enable
register). The Interrupt Status register is then read to determine which of the eight interrupts has been issued.
Channel
Selection
Data
000
001
010
011
100
101
110
111
Table 6. LM12(H)458 Input Multiplexer
Channel Configuration Showing Normal
Mode and Diagnostic Mode
V_IN+
Normal Mode
V_IN−
Diagnostic Mode
V_IN+
V_IN−
IN0
GND
V_REFOUT
GND
IN1
IN1
V_REF+
V_REF−
IN2
IN2
IN2
IN2
IN3
IN3
IN3
IN3
IN4
IN4
IN4
IN4
IN5
IN5
IN5
IN5
IN6
IN6
IN6
IN6
IN7
IN7
IN7
IN7
Table 7. LM12454 Input Multiplexer
Channel Configuration
Channel Selection Data
MUX+
000
IN0
001
IN1
010
IN2
011
IN3
1XX
OPEN
NOTE: The LM12(H)454 is no longer available. Information shown for reference only.
MUX−
GND
IN1
IN2
IN3
OPEN
The Interrupt Status register, 1010 (A4–A1, BW = 0) or 1010x (A4–A0, BW = 1) must be cleared by reading it
after writing to the Interrupt Enable register. This removes any spurious interrupts on the INT pin generated
during an Interrupt Enable register access.
Interrupt 0 is generated whenever the analog input voltage on a selected multiplexer channel crosses a limit
while the LM12(H)454/8 are operating in the “watchdog” comparison mode. Two sequential comparisons are
made when the LM12(H)454/8 are executing a “watchdog” instruction. Depending on the logic state of Bit 9 in
the Instruction RAM's second and third sections, an interrupt will be generated either when the input signal's
magnitude is greater than or less than the programmable limits. (See the Instruction RAM, Bit 9 description.) The
Limit Status register will indicate which preprogrammed limit, #1 or #2 and which instruction was executing when
the limit was crossed.
Interrupt 1 is generated when the Sequencer reaches the instruction counter value specified in the Interrupt
Enable register's bits 8–10. This flag appears before the instruction's execution.
Interrupt 2 is activated when the Conversion FIFO holds a number of conversions equal to the programmable
value stored in the Interrupt Enable register's Bits 11–15. This value ranges from 0001 to 1111, representing 1 to
31 conversions stored in the FIFO. A user-programmed value of 0000 has no meaning. See Section 3.0 for more
FIFO information.
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