DLPC900 Datasheet, PDF (32/72 Pages) Texas Instruments – Digital Controller for Advanced Light Control

DLPC900
DLPS037A – OCTOBER 2014 – REVISED AUGUST 2015
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6.14 DMD Interface Switching Characteristics ⁽¹⁾
over recommended operating conditions, C_L (min timing) = 5 pF, C_L (max timing) = 50 pF (unless otherwise noted)
PARAMETER
FROM
TO
MIN MAX
DMD TIMING MODE 0 ⁽²⁾
t_w(H)
DMD strobe high pulse duration
N/A
DADSTRB
29
t_w(L)
DMD strobe low pulse duration
N/A
DADSTRB
29
Output data valid window,
DADADDR_(3:0)
T_odv-min DADADDR_(3:0), DADMODE_(1:0), DADSEL_(1:0) DADMODE_(1:0)
DADSTRB↑ ⁽¹⁾
–27
with respect to DADSTRB
DADSEL_(1:0)
Output data valid window,
DADADDR_(3:0)
T_odv-max DADADDR_(3:0), DADMODE_(1:0), DADSEL_(1:0) DADMODE_(1:0)
DADSTRB↑ ⁽¹⁾
27
with respect to DADSTRB
DADSEL_(1:0)
DMD TIMING MODE 1 ⁽²⁾
t_w(H)
DMD strobe pulse duration
N/A
DADSTRB
14
t_w(L)
DMD strobe low pulse duration
N/A
DADSTRB
14
Output data valid window,
DADADDR_(3:0)
T_odv-min DADADDR_(3:0), DADMODE_(1:0), DADSEL_(1:0) DADMODE_(1:0)
DADSTRB↑ ⁽¹⁾
–12
with respect to DADSTRB
DADSEL_(1:0)
Output data valid window,
DADADDR_(3:0)
T_odv-max DADADDR_(3:0), DADMODE_(1:0), DADSEL_(1:0) DADMODE_(1:0)
DADSTRB↑ ⁽¹⁾
12
with respect to DADSTRB
DADSEL_(1:0)
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
(1) DMD control signals are captured on the rising edge of DADSTRB within the DMD.
(2) The DMD timing mode is controlled by the controller firmware.
DADADDR_(3:0)
DADMODE_(1:0)
DADSEL_(1:0)
t_odv-min
t_odv-max
DADSTRB
50%
50%
t_w(H)
Figure 10. DMD Interface Timing
32
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