TPS65917-Q1_17 Datasheet, PDF (30/87 Pages) Texas Instruments – Power Management Unit (PMU) for Processor

TPS65917-Q1
SLVSCO4C – JULY 2015 – REVISED MARCH 2017
www.ti.com
5.2 Functional Block Diagram
VSYS
C1
VSYS
C5
C4
C2
Boot mode
selection
BOOT
PWRON
VIO
C3
Application
Processor
GPIO
signals
and
controls
POWERHOLD Control
RESET_IN ^inputs
NRESWARM
NSLEEP
I2C1_SCL_CLK
I2C1_SDA_SDI _I²_{C CNTL,}
I2C2_SCL_SCE ^{I2C DVS,}
I2C2_SDA_SDO ^{or SPI}
LDOVANA
LDOVRTC
Test and
VCC program
internal
supply
TPS65917-Q1
RESET_OUT
INT
Internal
Interrupt
events
SYNCDCDC
PLL
(Phase
synchronization
and dither)
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
ADCIN1
ENABLE2
PWRDOWN
REGEN1
RESET_IN
RESWARM
VBUS_SENSE
ENABLE1
I2C2_SDA_SDO
ENABLE2
REGEN1
SYNCDCDC
REGEN2
I2C2_SCL_SCE
REGEN3
POWERHOLD
NSLEEP
REGEN3
POWERGOOD
Control
outputs
VCCA
POR
VCCA
VSYS_LO
VCC_SENSE
VSYS_MON
VBUS_SENSE
VBUS_WKUP_UP
JTAG
DFT
OTP controller
OTP memory
Registers
Programmable
power sequencer
controller
ECO
PWM
DVS
Switch ON and
OFF
WDT
Thermal
monitoring
Thermal
shutdown
Hot die detection
VCC_SENSE
12-bit
ADC
ADCIN2
Grounds
EN
VSEL
RAMP
CLK1
SMPS1_IN
SMPS1 ^SMPS1_SW
3.5 A _{<SMPS1_GND>}
(DVS/AVS)
[Master]
Dual or
SMPS2_IN
Single phase SMPS2_SW
SMPS2
3.5 A
SMPS1_FDBK
(DVS/AVS) _{SMPS2_FDBK}
[Multi/Stand-
alone] _{<SMPS2_GND>}
CLK2
EN
VSEL
RAMP
SMPS3_IN
SMPS3
3A
(DVS/
AVS)
SMPS3_SW
SMPS3_FDBK
<SMPS3_GND>
CLK3
EN
VSEL
SMPS4
1.5 A
(AVS)
SMPS4_IN
SMPS4_SW
SMPS4_FDBK
<SMPS4_GND>
CLK4
EN
VSEL
SMPS5_IN
SMPS5
2A
(AVS)
SMPS5_SW
SMPS5_FDBK
<SMPS5_GND>
Internal
32-KHz
RC
Osc.
SYNCCLKOUT
VSYS
L1
C13 C8
VSYS
L2
C14
C9
VSYS
L3
C15
C10
VSYS
L4
C16
C11
VSYS
L5
C12
C17
Bypass
LDO1
300 mA
Bypass
LDO2
300 mA
LDO3
200 mA
LDO4
200 mA
Low noise
LDO5
100 mA
VCC internal
supply
Reference
and bias
VBG
REFGND
C7
VSYS
C18 C19
C20 C21
C22
C23
C24
30
Detailed Description
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