TLC2264A-Q1 Datasheet, PDF (30/37 Pages) Texas Instruments – Advanced LinCMOS™ RAIL-TO-RAIL OPERATIONAL ANPLIFIERS

TLC226xĆQ1, TLC226xAĆQ1
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Advanced LinCMOS RAILĆTOĆRAIL
OPERATIONAL AMPLIFIERS
SGLS189B − OCTOBER 2003 − REVISED APRIL 2008
APPLICATION INFORMATION
driving large capacitive loads
The TLC226x is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 58
and Figure 59 illustrate its ability to drive loads greater than 400 pF while maintaining good gain and phase
margins (R_null = 0).
A smaller series resistor (R_null) at the output of the device (see Figure 62) improves the gain and phase margins
when driving large capacitive loads. Figure 58 and Figure 59 show the effects of adding series resistances of
10 Ω, 20 Ω, 50 Ω, and 100 Ω. The addition of this series resistor has two effects: the first is that it adds a zero
to the transfer function and the second is that it reduces the frequency of the pole associated with the output
load in the transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the improvement in phase margin, equation 1 can be used.
ǒ Ǔ _{∆Θm1 + tan}^–1 _{2 × π × UGBW × Rnull × CL}
(1)
Where :
∆Θ_m1 + improvement inphasemargin
UGBW + unity-gain bandwidth frequency
R_null + output seriesresistance
C_L + load capacitance
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 60). To
use equation 1, UGBW must be approximated from Figure 60.
Using equation 1 alone overestimates the improvement in phase margin, as illustrated in Figure 61. The
overestimation is caused by the decrease in the frequency of the pole associated with the load, thus providing
additional phase shift and reducing the overall improvement in phase margin. The pole associated with the load
is reduced by the factor calculated in equation 2.
F
+
1
)
1
g_m × R_null
(2)
Where :
F + factor reducingfrequencyof pole
g_m + small-signal output transconductance (typically 4.83 × 10^{– 3} mhos)
R_null + output series resistance
For the TLC226x, the pole associated with the load is typically 7 MHz with 100-pF load capacitance. This value
varies inversely with C_L: at C_L = 10 pF, use 70 MHz, at C_L = 1000 pF, use 700 kHz, and so on.
Reducing the pole associated with the load introduces phase shift, thereby reducing phase margin. This results
in an error in the increase in phase margin expected by considering the zero alone (equation 1). Equation 3
approximates the reduction in phase margin due to the movement of the pole associated with the load. The
result of this equation can be subtracted from the result of the equation in equation 1 to better approximate the
improvement in phase margin.
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