MSP430FG4619 Datasheet, PDF (30/114 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
www.ti.com
5.23 USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-18
and Figure 5-19)
f_USCI
PARAMETER
USCI input clock frequency
TEST CONDITIONS
SMCLK, ACLK
Duty cycle = 50% ±10%
V_CC
MIN
MAX UNIT
f_SYSTEM MHz
t_SU,MI
SOMI input data setup time
2.2 V
110
ns
3V
75
t_HD,MI
iSOMI input data hold time
2.2 V
0
ns
3V
0
t_VALID,MO SIMO output data valid time
UCLK edge to SIMO valid, C_L = 20 pF
2.2 V
3V
30
ns
20
5.24 USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-20
and Figure 5-21)
t_STE,LEAD
PARAMETER
STE lead time
STE low to clock
TEST CONDITIONS
V_CC
2.2 V, 3 V
MIN TYP MAX UNIT
50
ns
t_STE,LAG
STE lag time
Last clock to STE high
2.2 V, 3 V
10
ns
t_STE,ACC
STE access time
STE low to SOMI data out
2.2 V, 3 V
50
ns
t_STE,DIS
STE disable time
STE high to SOMI high impedance
2.2 V, 3 V
50
ns
t_SU,SI
SIMO input data setup time
2.2 V
20
ns
3V
15
t_HD,SI
SIMO input data hold time
2.2 V
10
ns
3V
10
t_VALID,SO SOMI output data valid time
UCLK edge to SOMI valid, C_L = 20 pF
2.2 V
3V
75 110
ns
50 75
30
Specifications
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