AFE8221-Q1 Datasheet, PDF (30/59 Pages) Texas Instruments – DUAL INTERMEDIATE FREQUENCY (IF) ANALOG FRONT-END FOR DIGITAL RADIO

AFE8221-Q1
SBAS434 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
Table 13. Third-Overtone Operation Recommendations
FREQUENCY (MHz)
55
60
65
70
75
C₁
C₂
L1
L2
R₁
(pF) (pF) (µH) (µH) (kΩ)
3
10 0.1 4.7 6.8
5
10 0.82 3.3 4.7
4
10 0.68 2.7 3.3
5
10 0.56 2.7 3.3
3
10 0.56 2.2 3.3
The master clock oscillator may be optionally divided down to provide a reference clock on the REFCLK pin.
Control variable refclk_en enables the generation of the reference clock when high. Two variables, refclk_hi and
refclk_lo, define the high and low periods of REFCLK in terms of MCLK cycles. REFCLK is high for refclk_hi
cycles of MCLK, then low for refclk_lo periods of MCLK. REFCLK frequency is limited to integer submultiples of
MCLK. Table 14 shows the refclk operation control settings.
Table 14. REFCLK Control Register Settings
PARAMETER
refclk_en
refclk_hi
refclk_lo
ADDRESS
1
41
40
BITS
13
15:0
15:0
Real-Time Clock Oscillator
The real-time clock oscillator supports crystals in the frequency range of 32.768 kHz through 150 kHz. The
real-time clock module can be programmed to operate accurately with crystals in this frequency range.
The real-time clock oscillator output may be optionally output on the RTC_OUT pin when rtc_oe is set high. This
option allows the real-time clock oscillator to be used as an alternate reference clock in the event that an
acceptable frequency cannot be derived from MCLK. Table 15 shows the rtc_oe control setting.
Table 15. RTC Control Register Setting
PARAMETER
rtc_oe
ADDRESS
1
BITS
12
I²C Master
The I²C Master interface uses control variables (as shown in Table 16) and two 16-byte buffers to create I²C bus
transactions compliant with the Philips I²C-Bus Specification Version 2.1. Both 7- and 10-bit addressing schemes
are supported. Control variables supply address, data transfer direction, data burst length, and transaction
control information to an I²C master engine. This engine handles the details of the I²C signaling and uses two
16-byte buffers to store data transferred during the transaction. A block diagram for this interface is illustrated in
Figure 19.
SCL clock rates are controlled using the i2cm_clk_cycles control variable given by Equation 24.
f_SCL =
f_MCLK
4 ´ i2cm_clk_cycles
(24)
The interface supports both standard and fast-mode clock rates of 100 kHz and 400 kHz, respectively. Although
two pairs of SCL and SDA pins are provided, the pins share a common master function. Reprogramming of the
i2cm_if_select variable should only be performed when the i2cm_done status is 1, indicating that all pending I²C
transactions have completed and that it is safe to change the selected pair.
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