TMS320F28030_17 Datasheet, PDF (3/161 Pages) Texas Instruments – Piccolo Microcontrollers

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TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584K – APRIL 2009 – REVISED JUNE 2016
1.4 Functional Block Diagram
Figure 1-1 shows the functional block diagram for the device.
M0
SARAM 1K × 16
(0-wait)
M1
SARAM 1K × 16
(0-wait)
Boot-ROM
8K × 16
(0-wait)
SARAM
4K/6K/8K × 16
(CLA Only on
28033 and 28035)
(0-wait)
Secure
Code
Security
Module
OTP 1K × 16
Secure
FLASH
16K/32K/64K × 16
Secure
PSWD
OTP/Flash
Wrapper
CLA
GPIO
MUX
AIO
MUX
COMP1OUT
COMP2OUT
COMP3OUT
COMP1A
COMP1B
COMP2A
COMP2B
COMP3A
COMP3B
COMP
A7:0
B7:0
ADC
Memory Bus
C28x
32-Bit CPU
TRST
TCK
TDI
TMS
TDO
GPIO
Mux
PIE
CPU Timer 0
CPU Timer 1
CPU Timer 2
OSC1,
OSC2,
Ext,
PLL,
LPM,
WD
Memory Bus
3 External Interrupts
XCLKIN
X1
X2
LPM Wakeup
XRS
POR/
BOR
VREG
16-Bit Peripheral Bus
32-Bit Peripheral Bus
(CLA-Accessible)
SCI
(4L FIFO)
SPI
(4L FIFO)
I2C
(4L FIFO)
ePWM
HRPWM
32-Bit Peripheral Bus
LIN eCAP
eQEP
eCAN
(32-mail HRCAP
box)
From
COMP1OUT,
COMP2OUT,
COMP3OUT
GPIO MUX
Copyright © 2016, Texas Instruments Incorporated
A. Not all peripheral pins are available at the same time due to multiplexing.
Figure 1-1. Functional Block Diagram
Copyright © 2009–2016, Texas Instruments Incorporated
Device Overview
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TMS320F28035