TLC5940-EP Datasheet, PDF (3/33 Pages) Texas Instruments – 16-CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL

TLC5940-EP
www.ti.com
SLVSA51D – MARCH 2010 – REVISED MAY 2010
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
q_JA
q_JC(TOP)
q_JC(BOTTOM)
q_JB
Ψ_JT
Ψ_JB
THERMAL METRIC⁽¹⁾
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-case (bottom) thermal resistance⁽⁴⁾
Junction-to-board thermal resistance⁽⁵⁾
Junction-to-top characterization parameter⁽⁶⁾
Junction-to-board characterization parameter⁽⁷⁾
RHB
32 PINS
33.9
30
3.9
9.3
0.619
9.3
PWP
28 PINS
35.4
24.94
5.37
15.02
1.297
10.96
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction to case (bottom) thermal resistance is obtained by simulations of this device as configured per MilStd 883 method 1012.1.
(5) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(6) The junction-to-top characterization parameter, Ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-board characterization parameter, Ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q_JA, using a procedure described in JESD51-2a (sections 6 and 7).
ABSOLUTE MAXIMUM RATINGS.
over operating free-air temperature range (unless otherwise noted)^{(1) (2)}
V_I Input voltage range⁽³⁾
I_O Output current (dc)
V_I Input voltage range
V_O Output voltage range
EEPROM program range
EEPROM write cycles
VCC
V_(BLANK), V_(DCPRG), V_(SCLK), V_(XLAT), V_(SIN), V_(GSCLK), V_(IREF)
V_(SOUT), V_(XERR)
V_(OUT0) to V_(OUT15)
V_(VPRG)
ESD rating
HBM (JEDEC JESD22-A114, Human Body Model)
CBM (JEDEC JESD22-C101, Charged Device Model)
T_stg Storage temperature range
T_A Operating ambient temperature range
Package thermal impedance
UNIT
–0.3V to 6V
130mA
–0.3V to V_CC +0.3V
–0.3V to V_CC +0.3V
–0.3V to 18V
–0.3V to 24V
25
2kV
500V
–55°C to 150°C
–40°C to 125°C
See Thermal Characteristics table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of
overall device life. See www.ti.com/ep_quality for additional information on enhanced plastic packaging.
(3) All voltage values are with respect to network ground terminal.
Copyright © 2010, Texas Instruments Incorporated
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