TLC5940-EP Datasheet, PDF (21/33 Pages) Texas Instruments – 16-CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL

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VPRG
GS Data Input Mode
TLC5940-EP
SLVSA51D – MARCH 2010 – REVISED MAY 2010
XLAT
SIN
1st GS Data Input Cycle
GS1
MSB
SCLK
1
SOUT ^-
-
BLANK
GS1
LSB
192
tsuLOD
GS1
MSB
2nd GS Data Input Cycle
GS2
MSB
> tpd4 + 15 x td + tpd3
193
1
GS2
LSB
192
SID1 SID1
MSB MSB-1
SID1 GS2
LSB MSB
(1st GS Data Output Cycle)
GSCLK
1
4096
OUT0
(current)
OUT1
(current)
OUT15
(current)
tpd3
td
15 x td
tpd2
XERR
tpd3 + 15 x td + tpd2
Figure 21. Readout Status Information Data (SID) Timing Chart
GRAYSCALE PWM OPERATION
The grayscale PWM cycle starts with the falling edge of BLANK. The first GSCLK pulse after BLANK goes low
increases the grayscale counter by one and switches on all OUTn with grayscale value not zero. Each following
rising edge of GSCLK increases the grayscale counter by one. The TLC5940 compares the grayscale value of
each output OUTn with the grayscale counter value. All OUTn with grayscale values equal to the counter values
are switched off. A BLANK=H signal after 4096 GSCLK pulses resets the grayscale counter to zero and
completes the grayscale PWM cycle (see Figure 22). When the counter reaches a count of FFFh, the counter
stops counting and all outputs turn off. Pulling BLANK high before the counter reaches FFFh immediately resets
the counter to zero.
Copyright © 2010, Texas Instruments Incorporated
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