TL750M05-Q1 Datasheet, PDF (3/23 Pages) Texas Instruments – AUTOMOTIVE LOW-DROPOUT VOLTAGE REGULATORS

TL750Mxx-Q1, TL751Mxx-Q1
www.ti.com
SGLS312J – SEPTEMBER 2005 – REVISED JUNE 2011
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)⁽¹⁾
Continuous input voltage
26 V
Transient input voltage (see Figure 4)
60 V
Continuous reverse input voltage
–15 V
Transient reverse input voltage
t = 100 ms
–50 V
θ_JA
Package thermal impedance^{(2) (3)}
KTT package (3 pin)
KTT package (5 pin)
KVU package
26.9°C/W
26.5°C/W
38.6°C/W
T_J
Virtual junction temperature range
T_stg
Storage temperature range
–40°C to 150°C
–65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Maximum power dissipation is a function of T_J(max), θ_JA, and T_A. The maximum allowable power dissipation at any allowable ambient
temperature is P_D = (T_J(max) – T_A)/θ_JA. Operating at the absolute maximum T_J of 150°C can impact reliability. Due to variation in
individual device electrical characteristics and thermal resistance, the built-in thermal overload protection may be activated at power
levels slightly above or below the rated dissipation.
(3) The package thermal impedance is calculated in accordance with JESD 51.
THERMAL INFORMATION
THERMAL METRIC⁽¹⁾
TL750M05
KTT
UNITS
θ_JA
θ_JCtop
θ_JB
ψ_JT
ψ_JB
θ_JCbot
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
Junction-to-case (bottom) thermal resistance⁽⁷⁾
3 PINS
27.5
43.2
17.3
2.8
9.3
0.3
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
V_I
Input voltage
V_IH
High-level ENABLE input voltage
V_IL
Low-level ENABLE input voltage
I_O
Output current
T_J
Operating virtual junction temperature
TL75xM05
TL75xM08
TL75xM12
TL751Mxx
TL751Mxx
TL75xMxx
TL75xMxx
MIN
MAX UNIT
6
26
9
26 V
13
26
2
15 V
0
0.8 V
750 mA
–40
125 °C
Copyright © 2005–2011, Texas Instruments Incorporated
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