LP8728-Q1 Datasheet, PDF (3/18 Pages) Texas Instruments – LP8728-Q1 Quad-Output Step-Down DC/DC Converter

LP8728-Q1
www.ti.com
SNVS972 – AUGUST 2013
ELECTRICAL CHARACTERISTICS⁽¹⁾⁽²⁾
Typical values and limits appearing in normal type apply for T_A = 25ºC. Unless otherwise noted, V_IN = 5.0 V. Limits appearing
in boldface type apply over junction temperature range, T_J = –40 ºC to 125ºC.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
I_SHDN
Shutdown Supply Current into
Power Connections
EN_Bx = 0V
1.0
6 μA
I_OP
Operating Current
LOGIC INPUTS (EN_Bx, DEFSEL)
All buck-converters active, I_OUT = 0mA
20
mA
V_IL
V_IH
R_{PD_DI}
Input Low Level
Input High Level
EN_Bx and DEFSEL Internal Pull-
down Resistance
0.4 V
1.6
V
300
520
820 kΩ
T_{H_MIN} Minimum EN_Bx High Time
T_{L_MIN} Minimum EN_Bx Low Time
LOGIC OUTPUTS (PG_Bx)
1
ms
10
µs
V_OL
Output Low Level
R_PU
Recommended Pull-up Resistor
BUCK CONVERTERS
I_SINK = 3mA
0.4 V
10
kΩ
V_OUT1
V_OUT2
V_OUT3
Output Voltage for Buck 1
Output Voltage for Buck 2
Output Voltage for Buck 3
Fixed voltage
Fixed voltage
DEFSEL = 1
DEFSEL = 0
3.3
V
1.25
V
2.65
V
1.8
V_OUT4
V_{FB_Bx}
ΔV_OUT
I_OUT
F_SW
GBW
Output Voltage for Buck 4
Output voltage accuracy
Line Regulation
Load Regulation
Output Current
Switching Frequency
Gain Bandwidth
Fixed voltage
4.5 V ≤ V_{IN_Bx} ≤ 5.5 V I_LOAD = 10 mA
V_IN = 5.0 V 100 mA ≤ I_LOAD ≤ 900 mA
DC load
1.8
V
–3
3%
3
mV
3
mV
1000 mA
3.03
3.2 3.37 MHz
300
kHz
I_LIMITP
I_LIMITN
R_DSONP
R_DSONN
I_{LK_SW}
R_{PD_FB}
High Side Switch Current Limit
Low Side Switch Current Limit
Pin-Pin Resistance for PFET
Pin-Pin Resistance for NFET
Switch Pin Leakage Current
Pull-down Resistor from FB_Bx pin
to GND
Reverse current
I_OUT = 200 mA
I_OUT = 200 mA
V_OUT = 1.8V
Only active when converter disabled.
1200 1500 1800 mA
500
mA
210
300 mΩ
140
240 mΩ
1 µA
40
70
100 Ω
K_RAMP Slew Rate Control
T_START Startup Time
K_START Soft-Start VOUT Slew Rate
VOLTAGE MONITORING
DEFSEL from 0 to 1
Time from first EN_Bx high to start of switching
10
mV/µs
420
µs
18
mV/µs
Power good threshold for voltage rising
V_PG
Power Good Threshold Voltage
Power good threshold for voltage falling
93.5
96
98 %
91
93
95 %
V_OVP
Input Over-voltage Protection
Trigger Point
Voltage monitored on AVDD Pin, voltage rising
Hysteresis
5.5
5.7
5.9 V
80
mV
V_UVLO
Input Under-voltage Lockout
(UVLO) turn-on threshold.
Voltage monitored on AVDD Pin, voltage falling
Hysteresis
4.35
V
80
mV
(1) All voltage values are with respect to network ground terminal.
(2) Min and Max limits are specified by design, test, or statistical analysis. Typical (Typ) numbers are not verified, but do represent the most
likely norm. Unless otherwise specified, conditions for Typ specifications are: V_IN = 5.0 V and T_J = 25ºC.
Copyright © 2013, Texas Instruments Incorporated
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