LP2998 Datasheet, PDF (3/33 Pages) Intersil Corporation – DDR-II and DDR-I Termination Regulator

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6 Pin Configuration and Functions
LP2998, LP2998-Q1
SNVS521K – DECEMBER 2007 – REVISED AUGUST 2014
SO PowerPAD
8-LEAD DDA
TOP VIEW
GND ¹
SD ²
VSENSE ³
VREF ⁴
GND
8 VTT
7 _PVIN
6 _AVIN
5 _VDDQ
SOIC
8-LEAD D
TOP VIEW
GND ¹
SD ²
VSENSE ³
VREF ⁴
8 VTT
7 _PVIN
6 _AVIN
5 _VDDQ
PIN
NUMBER
TYPE
1
GND
2
SD
3
VSENSE
4
VREF
5
VDDQ
6
AVIN
7
PVIN
8
VTT
EP
Pin Functions
DESCRIPTION
Ground
Shutdown
Feedback pin for regulating V_TT.
Buffered internal reference voltage of V_DDQ/2
Input for internal reference equal to V_DDQ/2
Analog input pin
Power input pin
Output voltage for connection to termination resistors
Exposed pad thermal connection. Connect to Ground.
6.1 Pin Descriptions
AVIN AND PVIN
VDDQ
AVIN and PVIN are the input supply pins for the LP2998. AVIN is used to supply all the internal control circuitry. PVIN,
however, is used exclusively to provide the rail voltage for the output stage used to create VTT. These pins have the
capability to work off separate supplies depending on the application. Higher voltages on PVIN will increase the
maximum continuous output current because of output RDSON limitations at voltages close to VTT. The disadvantage
of high values of PVIN is that the internal power loss will also increase, thermally limiting the design. For SSTL-2
applications, a good compromise would be to connect the AVIN and PVIN directly together at 2.5 V. This eliminates the
need for bypassing the two supply pins separately. The only limitation on input voltage selection is that PVIN must be
equal to or lower than AVIN. It is recommended to connect PVIN to voltage rails equal to or less than 3.3 V to prevent
the thermal limit from tripping because of excessive internal power dissipation. If the junction temperature exceeds the
thermal shutdown than the part will enter a shutdown state identical to the manual shutdown where V_TT is tri-stated and
V_REF remains active.
VDDQ is the input used to create the internal reference voltage for regulating V_TT. The reference voltage is generated
from a resistor divider of two internal 50 kΩ resistors. This ensures that V_TT will track VDDQ / 2 precisely. The optimal
implementation of VDDQ is as a remote sense. This can be achieved by connecting VDDQ directly to the 2.5 V rail at
the DIMM instead of AVIN and PVIN. This ensures that the reference voltage tracks the DDR memory rails precisely
without a large voltage drop from the power lines. For SSTL-2 applications VDDQ will be a 2.5 V signal, which will
create a 1.25 V termination voltage at V_TT (See Electrical Characteristics Table for exact values of V_TT over
temperature).
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Product Folder Links: LP2998 LP2998-Q1
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