LP2995 Datasheet, PDF (3/24 Pages) National Semiconductor (TI) – DDR Termination Regulator

LP2995
www.ti.com
SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings ⁽¹⁾⁽²⁾
AVIN to GND
PVIN to GND
VDDQ ⁽³⁾
Storage Temp. Range
Junction Temperature
SO PowerPAD-8 Thermal Resistance (θ_JA)
SOIC-8 Thermal Resistance (θ_JA)
WQFN-16 Thermal Resistance (θ_JA)
Lead Temperature (Soldering, 10 sec)
ESD Rating ⁽⁴⁾
−0.3V to +6V
-0.3V to AVIN
−0.3V to +6V
−65°C to +150°C
150°C
43°C/W
151°C/W
51°C/W
260°C
1kV
(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which
the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and test conditions
see Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) VDDQ voltage must be less than 2 x (AVIN - 1) or 6V, whichever is smaller.
(4) The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
Operating Range
Junction Temp. Range ⁽¹⁾
AVIN to GND
PVIN to GND
0°C to +125°C
2.2V to 5.5V
2.2V to AVIN
(1) At elevated temperatures, devices must be derated based on thermal resistance. The device in the SOIC-8 package must be derated at
θ_JA = 151° C/W junction to ambient with no heat sink. The device in the WQFN-16 must be derated at θ_JA = 51° C/W junction to
ambient.
Electrical Characteristics
Specifications with standard typeface are for T_J = 25°C and limits in boldface type apply over the full Operating
Temperature Range (T_J = 0°C to +125°C). Unless otherwise specified, AVIN = PVIN = 2.5V, VDDQ = 2.5V⁽¹⁾.
Symbol
Parameter
Conditions
Min
Typ
Max
V_REF
VOS_VTT
V_REF Voltage
V_TT Output Voltage Offset
I_{REF_OUT} = 0mA
I_OUT = 0A
(2)
1.21
1.235
1.26
−15
0
15
−20
20
ΔV_TT/V_TT
Z_VREF
Z_VDDQ
I_q
Load Regulation
(3)
V_REF Output Impedance
VDDQ Input Impedance
Quiescent Current
I_OUT = 0 to 1.5A
I_OUT = 0 to −1.5A
I_REF = −5µA to +5µA
I_OUT = 0A
(4)
0.5
−0.5
5
100
250
400
Units
V
mV
%
kΩ
kΩ
µA
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL).
(2) V_TT offset is the voltage measurement defined as V_TT subtracted from V_REF.
(3) Load regulation is tested by using a 10ms current pulse and measuring V_TT.
(4) Quiescent current defined as the current flow into AVIN.
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: LP2995
Submit Documentation Feedback
3