DS91M040_16 Datasheet, PDF (3/20 Pages) Texas Instruments – 125 MHz Quad M-LVDS Transceiver

DS91M040
www.ti.com
Number
1, 3, 5, 7
26, 28, 13, 15
25, 27, 14, 16
2, 4, 6, 8
31, DAP
17, 19, 21, 23
18, 20, 22, 24
11, 12, 29, 30
32
Name
RO
RE
DE
DI
GND
A
B
V_DD
FSEN1
9
FSEN2
10
MDE
SNLS283M – FEBRUARY 2008 – REVISED APRIL 2013
PIN DESCRIPTIONS
I/O, Type
Description
O, LVCMOS Receiver output pin.
I, LVCMOS
Receiver enable pin: When RE is high, the receiver is disabled. When RE is
low, the receiver is enabled. There is a 300 kΩ pullup resistor on this pin.
I, LVCMOS
Driver enable pin: When DE is low, the driver is disabled. When DE is high, the
driver is enabled. There is a 300 kΩ pulldown resistor on this pin.
I, LVCMOS Driver input pin.
Power
Ground pin and pad.
I/O, M-LVDS Non-inverting driver output pin/Non-inverting receiver input pin
I/O, M-LVDS Inverting driver output pin/Inverting receiver input pin
Power
Power supply pin, +3.3V ± 0.3V
I, LVCMOS
Failsafe enable pin with a 300 kΩ pullup resistor. This pin enables Type 2
receiver on inputs 0 and 2.
FSEN1 = L --> Type 1 receiver inputs
FSEN1 = H --> Type 2 receiver inputs
I, LVCMOS
Failsafe enable pin with a 300 kΩ pullup resistor. This pin enables Type 2
receiver on inputs 1 and 3.
FSEN2 = L --> Type 1 receiver inputs
FSEN2 = H --> Type 2 receiver inputs
I, LVCMOS
Master enable pin. When MDE is H, the device is powered up. When MDE is L,
the device overrides all other control and powers down.
M-LVDS Receiver Types
The EIA/TIA-899 M-LVDS standard specifies two different types of receiver input stages. A type 1 receiver has a
conventional threshold that is centered at the midpoint of the input amplitude, V_ID/2. A type 2 receiver has a built
in offset that is 100mV greater then V_ID/2. The type 2 receiver offset acts as a failsafe circuit where open or short
circuits at the input will always result in the output stage being driven to a low logic state.
Type 1
Type 2
2.4 V
xxxxxxxx High
V_ID
High
150 mV
50 mV
0V
-50 mV
Low
Low
-2.4 V
Transition Region
Figure 1. M-LVDS Receiver Input Thresholds
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS91M040
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