DRV8840_15 Datasheet, PDF (3/28 Pages) Texas Instruments – DC Motor Driver IC

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5 Pin Configuration and Functions
DRV8840
SLVSAB7D – MAY 2010 – REVISED DECEMBER 2015
CP1 1
CP2 2
VCP 3
VM 4
OUT1 5
ISEN 6
OUT2 7
OUT2 8
ISEN 9
OUT1 10
VM 11
VREF 12
VREF 13
GND 14
PWP Package
28-Pin HTSSOP
Top View
GND
(PPAD )
28 GND
27 I4
26 I3
25 I2
24 I1
23 I0
22 NC
21 ENBL
20 PHASE
19 DECAY
18 nFAULT
17 nSLEEP
16 nRESET
15 V3P3OUT
PIN
NAME
NO.
POWER AND GROUND
GND
14, 28
VM
4, 11
V3P3OUT
15
CP1
1
CP2
2
VCP
3
CONTROL
PHASE
20
ENBL
21
I0
23
I1
24
I2
25
I3
26
I4
27
DECAY
19
nRESET
16
nSLEEP
17
VREF
12,13
I/O ⁽¹⁾
Pin Functions
DESCRIPTION
—
Device ground
—
Bridge A power supply
O
3.3-V regulator output
IO
Charge pump flying capacitor
IO
Charge pump flying capacitor
IO
High-side gate drive voltage
I
Bridge phase (direction)
I
Bridge enable
I
I
I
Current set inputs
I
I
I
Decay (brake) mode
I
Reset input
I
Sleep mode input
I
Current set reference input
EXTERNAL COMPONENTS
OR CONNECTIONS
Connect to motor supply (8.2 - 45 V). Both
pins must be connected to same supply.
Bypass to GND with a 0.47-μF, 6.3-V ceramic
capacitor. Can be used to supply VREF.
Connect a 0.01-μF 50-V capacitor between
CP1 and CP2.
Connect a 0.1-μF 16-V ceramic capacitor and
a 1-MΩ resistor to VM.
Logic high sets OUT1 high, OUT2 low.
Internal pulldown.
Logic high to enable H-bridge. Internal
pulldown.
Sets winding current as a percentage of full-
scale. Internal pulldown.
Low = brake (slow decay), high = coast (fast
decay). Internal pulldown and pullup.
Active-low reset input initializes the logic and
disables the H-bridge outputs. Internal
pulldown.
Logic high to enable device, logic low to enter
low-power sleep mode. Internal pulldown.
Reference voltage for winding current set.
Both pins must be connected together on the
PCB.
(1) Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output
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