DRV8814_16 Datasheet, PDF (3/26 Pages) Texas Instruments – DC Motor Driver IC

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5 Pin Configuration and Functions
DRV8814
SLVSAB9E – MAY 2010 – REVISED NOVEMBER 2015
PWP Package
28-Pin HTSSOP with PowerPAD™
Top View
PIN
NAME
NO.
POWER AND GROUND
GND
14, 28
VMA
4
I/O ⁽¹⁾
-
-
VMB
11
-
V3P3OUT
15
O
CP1
1
IO
CP2
2
IO
VCP
3
IO
CONTROL
AENBL
21
I
APHASE
20
I
AI0
24
I
AI1
25
I
BENBL
22
I
BPHASE
23
I
BI0
26
I
BI1
27
I
DECAY
19
I
nRESET
16
I
nSLEEP
17
I
AVREF
BVREF
12
I
13
I
Pin Functions
DESCRIPTION
EXTERNAL COMPONENTS
OR CONNECTIONS
Device ground
Bridge A power supply
Bridge B power supply
3.3-V regulator output
Charge pump flying capacitor
Charge pump flying capacitor
High-side gate drive voltage
Connect to motor supply (8 V to 45 V). Both pins must be
connected to the same supply, bypassed with a 0.1-µF
capacitor to GND, and connected to appropriate bulk
capacitance.
Bypass to GND with a 0.47-μF 6.3-V ceramic capacitor. Can be
used to supply VREF.
Connect a 0.01-μF 50-V capacitor between CP1 and CP2.
Connect a 0.1-μF 16-V ceramic capacitor and a 1-MΩ to VM.
Bridge A enable
Bridge A phase (direction)
Logic high to enable bridge A
Logic high sets AOUT1 high, AOUT2 low
Bridge A current set
Sets bridge A current: 00 = 100%, 01 = 71%, 10 = 38%, 11 = 0
Bridge B enable
Bridge B phase (direction)
Logic high to enable bridge B
Logic high sets BOUT1 high, BOUT2 low
Bridge B current set
Sets bridge B current: 00 = 100%, 01 = 71%, 10 = 38%, 11 = 0
Decay (brake) mode
Reset input
Sleep mode input
Bridge A current set reference input
Bridge B current set reference input
Low = brake (slow decay), high = coast (fast decay)
Active-low reset input initializes internal logic and disables the
H-bridge outputs
Logic high to enable device, logic low to enter low-power sleep
mode
Reference voltage for winding current set. Can be driven
individually with an external DAC for microstepping, or tied to a
reference (e.g., V3P3OUT).
(1) Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output
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