CDC9171 Datasheet, PDF (3/5 Pages) Texas Instruments – DVD SYSTEM CLOCK SYNTHESIZER

CDC9171
DVD SYSTEM CLOCK SYNTHESIZER
recommended operating conditions (see Note 3)
VCC Supply voltage
VI
Input voltage (PWRDN only)
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
SCAS558B – DECEMBER 1995 – REVISED OCTOBER 1996
MIN MAX UNIT
3 3.6 V
0 5.5 V
2
V
0.8 V
–8 mA
8 mA
0
70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VOH
VOL
II†
VCC = 3 V,
VCC = 3 V,
VCC = 3 V,
VCC = 3.6 V,
ICC
VCC = 3.6 V,
VI = VCC or GND
Ci†
VI = 3 V or 0
Co
VO = 3 V or 0
† _{Except for crystal input (1X1)}
II = –18 mA
IOH = –8 mA
IOL = 8 mA
VI = VCC or GND
Outputs active
IO = 0
(PWRDN = H)
Outputs low
(PWRDN = L)
TA = 25°C
MIN TYP MAX
–1.2
2.4
0.4
±1
20
35
5
10
7
8
MIN MAX UNIT
–1.2 V
2.4
V
0.4 V
±1 µA
35
mA
10
pF
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN MAX UNIT
Stabilization time‡
After PWRDN ↑
After power up
5
ms
5
‡ _{Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a}
fixed-frequency, fixed-phase reference signal must be present at 1X1.
switching characteristics over recommended free-air temperature range for 3-V outputs (see
Figure 1)^§
PARAMETER
Jitter
FCLK1
All other outputs
Duty cycle
Any output
tr¶
Any output (CL = 20 pF)
tf¶
Any output (CL = 20 pF)
§ _{Specifications are applicable only after the PLL stabilization time has elapsed.}
¶ _{Rise and fall times are characterized using the test circuit shown in Figure 1.}
VCC = 3.3 V,
TA = 25°C
MIN MAX
VCC = 3 V to 3.6 V,
TA = 0°C to 70°C
MIN
MAX
±200
±250
45%
55%
2.5
2.5
UNIT
ps
ns
ns
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