74ACT11074_14 Datasheet, PDF (3/14 Pages) Texas Instruments – DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

74ACT11074
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCAS498A – DECEMBER 1986 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN TYP MAX
MIN MAX
IOH = –50 mA
4.5 V 4.4
4.4
5.5 V 5.4
5.4
VOH
IOH = –24 mA
4.5 V 3.94
3.8
5.5 V 4.94
4.8
IOH = –75 mA†
IOL = 50 mA
5.5 V
4.5 V
5.5 V
3.85
0.1
0.1
0.1
0.1
VOL
IOL = 24 mA
4.5 V
5.5 V
0.36
0.44
0.36
0.44
II
ICC
DICC‡
IOL = 75 mA†
VI = VCC or GND
VI = VCC or GND,
One input at 3.4 V,
IO = 0
Other inputs at GND or VCC
5.5 V
5.5 V
5.5 V
5.5 V
1.65
±0.1
±1
4
40
0.9
1
Ci
VI = VCC or GND
5V
3.5
† _{Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.}
‡ _{This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.}
UNIT
V
V
mA
mA
mA
pF
timing requirements over recommended ranges of supply voltage and free-air temperature (unless
otherwise noted) (see Figure 1)
fclock Clock frequency
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time after CLK↑
PRE or CLR low
CLK low or high
Data high or low
PRE or CLR inactive
TA = 25°C
MIN MAX
0 100
5
5
4.5
2
0
MIN MAX UNIT
0 100 MHz
5
ns
5
4.5
ns
2
0
ns
switching characteristics over recommended ranges of supply voltage and free-air temperature
(unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
PRE or CLR
CLK
TO
(OUTPUT)
Q or Q
Q or Q
TA = 25°C
MIN TYP MAX
100 125
1.5 5.7 8.9
1.5 6.6 11.3
1.5
6 8.5
1.5 5.7
8
MIN MAX UNIT
100
MHz
1.5 9.6
ns
1.5 12.5
1.5 9.4
ns
1.5 8.8
operating characteristics, V_CC = 5 V, T_A = 25°C
PARAMETER
Cpd Power dissipation capacitance per flip-flop
TEST CONDITIONS
CL = 50 pF, f = 1 MHz
TYP UNIT
30 pF
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