TPS65023_15 Datasheet, PDF (29/47 Pages) Texas Instruments – Power Management IC

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TPS65023, TPS65023B
SLVS670K – JUNE 2006 – REVISED DECEMBER 2015
For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start
condition and terminated with a stop condition. When addressed, the TPS65023x device generates an
acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra
clock pulse that is associated with the acknowledge bit. The TPS65023x device must pull down the DATA line
during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the
acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock
pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of
data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this
case, the slave TPS65023x device must leave the data line high to enable the master to generate the stop
condition. See I²C Timing Requirements for TPS65023B for more information.
DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 31. Bit Transfer on the Serial Interface
CE
DATA
CLK
S
START Condition
Figure 32. START and STOP Conditions
SCLK
P
STOP Condition
SDAT
A6 A5 A4
A0 R/W ACK
00
Start
Slave Address
R7 R6 R5
R0 ACK
0
Register Address
D7 D6 D5
D0 ACK
0
Data
Stop
Note: SLAVE = TPS65023
Figure 33. Serial I/F WRITE to TPS65023x Device
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Product Folder Links: TPS65023 TPS65023B