TPS65023_15 Datasheet, PDF (24/47 Pages) Texas Instruments – Power Management IC

TPS65023, TPS65023B
SLVS670K – JUNE 2006 – REVISED DECEMBER 2015
Feature Description (continued)
VSYSIN
VBACKUP
V_ref
V_VSYSIN
priority
#1
V_ref
V_VBACKUP
priority
#2
V_VSYSIN
V_VBACKUP
V_CC
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EN _VRTC
LDO
priority
#3
VRTC
RESPWRON
V_ref
A. V_VSYSIN, V_VBACKUP thresholds: falling = 2.55 V, rising = 2.65 V ±3%
B. RESPWRON thresholds: falling = 2.4 V, rising = 2.52 V ±3%
Figure 30. RTC and nRESPWRON
8.3.2 Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3
The TPS65023x incorporates three synchronous step-down converters operating typically at
2.25-MHz, fixed frequency pulse width modulation (PWM) at moderate to heavy-load currents. At light-load
currents, the converters automatically enter the power save mode (PSM), and operate with pulse frequency
modulation (PFM). The VDCDC1 converter is capable of delivering 1.5-A output current, the VDCDC2 converter
is capable of delivering 1.2 A and the VDCDC3 converter is capable of delivering up to 1 A.
The converter output voltages can be programmed through the DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins.
The pins can either be connected to GND, VCC, or to a resistor divider between the output voltage and GND.
The VDCDC1 converter defaults to 1.2 V or 1.6 V depending on the DEFDCDC1 configuration pin. If DEFDCDC1
is tied to ground, the default is 1.2 V. If it is tied to VCC, the default is 1.6 V. When the DEFDCDC1 pin is
connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC1 V. See
Application Information for more details. The core voltage can be reprogrammed through the serial interface in
the range of 0.8 V to 1.6 V with a programmable slew rate. The converter is forced into PWM operation whilst
any programmed voltage change is underway, whether the voltage is being increased or decreased. The
DEFCORE and DEFSLEW registers are used to program the output voltage and slew rate during voltage
transitions.
The VDCDC2 converter defaults to 1.8 V or 3.3 V depending on the DEFDCDC2 configuration pin. If DEFDCDC2
is tied to ground, the default is 1.8 V. If it is tied to VCC, the default is 3.3 V. When the DEFDCDC2 pin is
connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC2 V.
The VDCDC3 converter defaults to 1.8 V or 3.3 V depending on the DEFDCDC3 configuration pin. If DEFDCDC3
is tied to ground the default is 1.8 V. If it is tied to VCC, the default is 3.3 V. When the DEFDCDC3 pin is
connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC3 V.
The step-down converter outputs (when enabled) are monitored by power-good (PG) comparators, the outputs of
which are available through the serial interface. The outputs of the DC-DC converters can be optionally
discharged through on-chip 300-Ω resistors when the DC-DC converters are disabled.
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