TLC2252-EP Datasheet, PDF (29/38 Pages) Texas Instruments – Advanced LinCMOS™ RAIL-TO-RAIL VERY LOW-POWER OPERATIONAL AMPLIFIERS

ą
TLC225xĆEP, TLC225xAĆEP
Advanced LinCMOS RAILĆTOĆRAIL
VERY LOWĆPOWER OPERATIONAL AMPLIFIERS
SGLS216 − NOVEMBER 2003
APPLICATION INFORMATION
driving large capacitive loads
The TLC225x is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 56
and Figure 57 illustrate its ability to drive loads up to 1000 pF while maintaining good gain and phase margins
(R_null = 0).
A smaller series resistor (R_null) at the output of the device (see Figure 60) improves the gain and phase margins
when driving large capacitive loads. Figure 56 and Figure 57 show the effects of adding series resistances of
10 Ω, 50 Ω, 100 Ω, 200 Ω, and 500 Ω. The addition of this series resistor has two effects: the first is that it adds
a zero to the transfer function and the second is that it reduces the frequency of the pole associated with the
output load in the transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the improvement in phase margin, equation 1 can be used.
ǒ Ǔ _{∆φm1 + tan}^–1 _{2 × π × UGBW × Rnull × CL}
(1)
Where :
∆φ_m1 + Improvement in phase margin
UGBW + Unity-gain bandwidth frequency
R_null + Output series resistance
C_L + Load capacitance
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 58). To
use equation 1, UGBW must be approximated from Figure 58.
Using equation 1 alone overestimates the improvement in phase margin, as illustrated in Figure 59. The
overestimation is caused by the decrease in the frequency of the pole associated with the load, thus providing
additional phase shift and reducing the overall improvement in phase margin.
Using Figure 60, with equation 1 enables the designer to choose the appropriate output series resistance to
optimize the design of circuits driving large capacitance loads.
50 kΩ
VDD ₊
50 kΩ
VI
−
Rnull
+
CL
VDD _{−/ GND}
Figure 60. Series-Resistance Circuit
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
29