LMK04800 Datasheet, PDF (29/91 Pages) Texas Instruments – Low-Noise Clock Jitter Cleaner with Dual Loop PLLs

16.0 Functional Description
16.1 FUNCTIONAL OVERVIEW
In default mode of operation, dual PLL mode with internal
VCO, the Phase Frequency Detector in PLL1 compares the
active CLKinX reference divided by CLKinX_PreR_DIV and
PLL1 R divider with the external VCXO or crystal attached to
the PLL2 OSCin port divided by PLL1 N divider. The external
loop filter for PLL1 should be narrow to provide an ultra clean
reference clock from the external VCXO or crystal to the OS-
Cin/OSCin* pins for PLL2.
The Phase Frequency Detector in PLL2 compares the exter-
nal VCXO or crystal attached to the OCSin port divided by the
PLL2 R divider with the output of the internal VCO divided by
the PLL2 N divider and N2 pre-scaler and optionally the VCO
divider. The bandwidth of the external loop filter for PLL2
should be designed to be wide enough to take advantage of
the low in-band phase noise of PLL2 and the low high offset
phase noise of the internal VCO. The VCO output is also
placed on the distribution path for the clock distribution sec-
tion. The clock distribution consists of 6 groups of dividers and
delays which drive 12 outputs. Each clock group allows the
user to select a divide value, a digital delay value, and an
analog delay. The 6 groups drive programmable output
buffers. Two groups allow their input signal to be from the
OSCin port directly.
When a 0-delay mode is used, a clock output will be passed
through the feedback mux to the PLL1 N Divider for synchro-
nization and 0-delay.
When an external VCO mode is used, the Fin port will be used
to input an external VCO signal. PLL2 Phase comparison will
now be with this signal divided by the PLL2 N divider and N2
pre-scaler. The VCO divider may not be used. One less clock
input is available when using an external VCO mode.
When a single PLL mode is used, PLL1 is powered down.
OSCin is used as a reference to PLL2.
16.2 MODE SELECTION
The LMK04800 family is capable of operating in several dif-
ferent modes as programmed by Section 17.9.1 MODE: De-
vice Mode.
MODE
R11
[31:27]
0
2
3
5
6
8
11
16
TABLE 1. Device Mode Selection
PLL1 PLL2
PLL2
VCO
0-delay
X
X Internal
X
X Internal
X
X
X External
X
X External
X
X Internal
X Internal
X
X External
Clock
Dist
X
X
X
X
X
X
X
X
In addition to selecting the device's mode of operation above,
some modes require additional configuration. Also there are
other features including holdover and dynamic digital delay
that can also be enabled.
TABLE 2. Registers to Further Configure Device Mode of
Operation
Register
Holdover
0-Delay
Dynamic
Digital
Delay
HOLDOVER_MODE
2
—
—
EN_TRACK
User
—
—
DAC_CLK_DIV
User
—
—
EN_MAN_DAC
User
—
—
DISABLE_DLD1_DET User
—
—
EN_VTUNE_RAIL_
DET
User
—
—
DAC_HIGH_TRIP
User
—
—
DAC_LOW_TRIP
User
—
—
FORCE_HOLDOVER
0
—
—
SYNC_EN_AUTO
—
—
User
SYNC_QUAL
—
—
1
EN_SYNC
—
—
1
CLKout4_5_PD
—
—
0
EN_
FEEDBACK_MUX
—
1
1
FEEDBACK_MUX
Feedback Qualifying
—
Clock
Clock
NO_SYNC_
CLKoutX_Y
—
—
User
16.3 INPUTS / OUTPUTS
16.3.1 PLL1 Reference Inputs (CLKin0 and CLKin1)
The reference clock inputs for PLL1 may be selected from
either CLKin0 or CLKin1. The user has the capability to man-
ually select one of the inputs or to configure an automatic
switching mode of operation. See Section 16.4 INPUT
CLOCK SWITCHING for more info.
CLKin0 and CLKin1 have dividers which allow the device to
switch between reference inputs of different frequencies au-
tomatically without needing to reprogram the PLL1 R divider.
The CLKin pre-divider values are 1, 2, 4, and 8.
CLKin1 input can alternatively be used for external feedback
in 0-delay mode (FBCLKin) or for an external VCO input port
(Fin).
16.3.2 PLL2 OSCin / OSCin* Port
The feedback from the external oscillator being locked with
PLL1 drives the OSCin/OSCin* pins. Internally this signal is
routed to the PLL1 N Divider and to the reference input for
PLL2.
This input may be driven with either a single-ended or differ-
ential signal and must be AC coupled. If operated in single
ended mode, the unused input must be connected to GND
with a 0.1 µF capacitor.
16.3.3 CRYSTAL OSCILLATOR
The internal circuitry of the OSCin port also supports the op-
tional implementation of a crystal based oscillator circuit. A
crystal, a varactor diode, and a small number of other external
components may be used to implement the oscillator. The in-
ternal oscillator circuit is enabled by setting the
EN_PLL2_XTAL bit. See Section 17.9.9 EN_PLL2_XTAL.
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