LMK04800 Datasheet, PDF (27/91 Pages) Texas Instruments – Low-Noise Clock Jitter Cleaner with Dual Loop PLLs

15.0 Features
15.1 SYSTEM ARCHITECTURE
The dual loop PLL architecture of the LMK048xx provides the
lowest jitter performance over the widest range of output fre-
quencies and phase noise integration bandwidths. The first
stage PLL (PLL1) is driven by an external reference clock and
uses an external VCXO or tunable crystal to provide a fre-
quency accurate, low phase noise reference clock for the
second stage frequency multiplication PLL (PLL2). PLL1 typ-
ically uses a narrow loop bandwidth (10 Hz to 200 Hz) to retain
the frequency accuracy of the reference clock input signal
while at the same time suppressing the higher offset frequen-
cy phase noise that the reference clock may have accumu-
lated along its path or from other circuits. This “cleaned”
reference clock provides the reference input to PLL2.
The low phase noise reference provided to PLL2 allows PLL2
to operate with a wide loop bandwidth (50 kHz to 200 kHz).
The loop bandwidth for PLL2 is chosen to take advantage of
the superior high offset frequency phase noise profile of the
internal VCO and the good low offset frequency phase noise
of the reference VCXO or tunable crystal.
Ultra low jitter is achieved by allowing the external VCXO or
Crystal’s phase noise to dominate the final output phase noise
at low offset frequencies and the internal VCO’s phase noise
to dominate the final output phase noise at high offset fre-
quencies. This results in best overall phase noise and jitter
performance.
The LMK048xx allows subsets of the device to be used to
increase the flexibility of device. These different modes are
selected using Section 17.9.1 MODE: Device Mode. For in-
stance:
• Dual Loop Mode - Typical use case of LMK04808. CLKinX
used as reference input to PLL1, OSCin port is connected
to VCXO or tunable crystal.
• Single Loop Mode - Powers down PLL1. OSCin port is
used as reference input.
• Clock Distribution Mode - Allows input of CLKin1 to be
distributed to output with division, digital delay, and analog
delay.
See Functional Description for more information on these
modes.
15.2 PLL1 REDUNDANT REFERENCE INPUTS (CLKin0/
CLKin0* and CLKin1/CLKin1*)
The LMK0480x has two reference clock inputs for PLL1,
CLKin0 and CLKin1. Ref Mux selects CLKin0 or CLKin1. Au-
tomatic or manual switching occurs between the inputs.
CLKin0 and CLKin1 each have input dividers. The input di-
vider allows different clock input frequencies to be normalized
so that the frequency input to the PLL1 R divider remains
constant during automatic switching. By programming these
dividers such that the frequency presented to the input of the
PLL1_R divider is the same prevents the user from needing
to reprogram the PLL1 R divider when the input reference is
changed to another CLKin port with a different frequency.
CLKin1 is shared for use as an external 0-delay feedback
(FBCLKin), or for use with an external VCO (Fin).
Fast manual switching between reference clocks is possible
with a external pins Status_CLKin0 and Status_CLKin1.
15.3 PLL1 TUNABLE CRYSTAL SUPPORT
The LMK048xx integrates a crystal oscillator on PLL1 for use
with an external crystal and varactor diode to perform jitter
cleaning.
The LMK048xx must be programmed to enable Crystal mode.
15.4 VCXO/CRYSTAL BUFFERED OUTPUTS
The LMK048xx provides 2 dedicated outputs which are a
buffered copy of the PLL2 reference input. This reference in-
put is typically a low noise VCXO or Crystal. When using a
VCXO, this output can be used to clock external devices such
as microcontrollers, FPGAs, CPLDs, etc. before the
LMK048xx is programmed.
The OSCout0 buffer output type is programmable to LVDS,
LVPECL, or LVCMOS. The OSCout1 buffer is fixed to
LVPECL.
The dedicated output buffers OSCout0 and OSCout1 can
output frequency lower than the VCXO or Crystal frequency
by programming the OSC Divider. The OSC Divider value
range is 1 to 8. Each OSCoutX can individually choose to use
the OSC Divider output or to bypass the OSC Divider.
Two clock output groups can also be programmed to be driv-
en by OSCin. This allows a total of 4 additional differential
outputs to be buffered outputs of OSCin. When programmed
in this way, a total of 6 differential outputs can be driven by a
buffered copy of OSCin.
VCXO/Crystal buffered outputs cannot be synchronized to
the VCO clock distribution outputs. The assertion of SYNC
will still cause these outputs to become low. Since these out-
puts will turn off and on asynchronously with respect to the
VCO sourced clock outputs during a SYNC, it is possible for
glitches to occur on the buffered clock outputs when SYNC is
asserted and unasserted. If the NO_SYNC_CLKoutX_Y bits
are set these outputs will not be affected by the SYNC event
except that the phase relationship will change with the other
synchronized clocks unless a buffered clock output is used as
a qualification clock during SYNC.
15.5 FREQUENCY HOLDOVER
The LMK048xx supports holdover operation to keep the clock
outputs on frequency with minimum drift when the reference
is lost until a valid reference clock signal is re-established.
15.6 INTEGRATED LOOP FILTER POLES
The LMK048xx features programmable 3rd and 4th order
loop filter poles for PLL2. These internal resistors and capac-
itor values may be selected from a fixed range of values to
achieve either a 3rd or 4th order loop filter response. The in-
tegrated programmable resistors and capacitors compliment
external components mounted near the chip.
These integrated components can be effectively disabled by
programming the integrated resistors and capacitors to their
minimum values.
15.7 INTERNAL VCO
The output of the internal VCO is routed to a mux which allows
the user to select either the direct VCO output or a divided
version of the VCO for the Clock Distribution Path. This same
selection is also fed back to the PLL2 phase detector through
a prescaler and N-divider.
The mux selectable VCO divider has a divide range of 2 to 8
with 50% output duty cycle for both even and odd divide val-
ues.
The primary use of the VCO divider is to achieve divides
greater than the clock output divider supports alone.
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