BQ25895_16 Datasheet, PDF (29/67 Pages) Texas Instruments – Adjustable Voltage 3.1-A Boost Operation

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bq25895
SLUSC88A – MARCH 2015 – REVISED MAY 2016
8.2.15.3 System Overcurrent Protection
When the system is shorted or significantly overloaded (I_BAT > I_BATOP) so that its current exceeds the overcurrent
limit, the device latches off BATFET. Section BATFET Enable (Exit Shipping Mode) can reset the latch-off
condition and turn on BATFET
8.2.16 Serial Interface
The device uses I²C compatible interface for flexible charging parameter programming and instantaneous device
status reporting. I²C is a bi-directional 2-wire serial interface. Only two open-drain bus lines are required: a serial
data line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing
data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals
to permit that transfer. At that time, any device addressed is considered a slave.
The device operates as a slave device with address 6BH, receiving control inputs from the master device like
micro controller or a digital signal processor through REG00-REG14. Register read beyond REG14 (0x14)
returns 0xFF. The I²C interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits).
When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain and must be connected to the
positive supply voltage via a current source or pull-up resistor.
8.2.16.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each
data bit transferred.
SDA
SCL
Data line stable;
Data valid
Change
of data
allowed
Figure 17. Bit Transfer on the I²C Bus
8.2.16.2 START and STOP Conditions
All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the
SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered busy after the START
condition, and free after the STOP condition.
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