ADC14X250 Datasheet, PDF (29/69 Pages) Texas Instruments – MSPS Single Channel ADC

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Test Pattern
PRBS
ADC14X250
SLASE49 – DECEMBER 2015
Table 5. Supported Test Pattern Sequences (continued)
Description
Common Purpose
PRBS 7/15/23 Complies with ITU-T O.150 specification and is
compatible with J-BERT equipment
Jitter and bit error rate testing
8.3.11 JESD204B Link Initialization
A JESD204B link is established via link initialization, which involves the following steps: frame alignment, code
group synchronization, and initial lane synchronization. These steps are shown in Figure 36. Link initialization
must occur between the transmitting device (ADC14X250) and receiving device before sampled data may be
transmitted over the link. The link initialization steps described here are specifically for the ADC14X250 device,
supporting JESD204B subclass 1.
SYSREF assertion
latched
SYNCb
Serial Data
CLKIN
SYSREF
Tx Frame Clk
Tx LMFC Boundary
tS-SYS
XXX
tH-SYS
tPL-SYS
tPH-SYS
tD-LMFC
Frame Clock
Alignment
SYNCb assertion
latched
tS-SYNCb-F
XXX
tS-SYNCb
K28.5
tD-K28
SYNCb de-assertion
latched
tH-SYNCb-F
K28.5
tS-SYNCb-F
tILA
ILA
tD-ILA
ILA
tD-DATA
Valid Data
Code Group
Synchronization
Initial Frame and Lane
Synchronization
Data
Transmission
Figure 36. Link-initialization Timing and Flow Diagram
The Frame Alignment step requires alignment of the frame and local multi-frame clocks within the ADC14X250
device to an external reference. This is accomplished by providing the device clock and SYSREF clock to the
CLKIN and SYSREF inputs, respectively. The ADC14X250 device aligns its frame clock and LMFC to any
SYSREF rising edge event, offset by a SYSREF-to-LMFC propagation delay.
The SYSREF signal must be source synchronous to the device clock; therefore, the SYSREF rising edge must
meet setup and hold requirements relative to the signal at the CLKIN input. If these requirements cannot be met,
then the alignment of the internal frame and multi-frame clocks cannot be ensured. As a result, a link may still be
established, but the latency through the link cannot be deterministic. Frame alignment may occur at any time;
although, a re-alignment of the internal frame clock and LMFC will break the link. Note that frame alignment is
not required for the ADC14X250 device to establish a link because the device automatically generates the clocks
on power-up with unknown phase alignment.
Code Group Synchronization is initiated when the receiver sends a synchronization request by asserting the
SYNCb input of the ADC14X250 device to a logic low state (SYNCb+ < SYNCb–). After the SYNCb assertion is
detected, the ADC14X250 device outputs K28.5 symbols on all serial lanes that are used by the receiver to
synchronize and time align its clock and data recovery (CDR) block to the known symbols. The SYNCb signal
must be asserted for at least 4 frame clock cycles otherwise the event is ignored by the ADC14X250 device.
Code group synchronization is completed when the receiver de-asserts the SYNCb signal to a logic high state.
After the ADC14X250 detects a de-assertion of its SYNCb input, the Initial Lane Synchronization step begins
on the following LMFC boundary. The ADC14X250 device outputs 4 multi-frames of information that compose
the ILA sequence. This sequence contains information about the data transmitted on the link. The initial lane
synchronization step and link initialization conclude when the ILA is finished and immediately transitions into
Data Transmission. During data transmission, valid sampled data is transmitted across the link until the link is
broken.
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