ADC14X250 Datasheet, PDF (1/69 Pages) Texas Instruments – MSPS Single Channel ADC

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ADC14X250
SLASE49 – DECEMBER 2015
ADC14X250 14-Bit 250 MSPS Single Channel ADC With 5 Gb/s JESD204B Output
1 Features
•1 Resolution: 14-Bit
• Conversion Rate: 250 MSPS
• Performance:
– Input: 240 MHz, –3 dBFS
– SNR: 70.1 dBFS
– Noise Spectral Density: –151.1 dBFS/Hz
– SFDR: 87 dBFS
– Non-HD2 and Non-HD3 SPUR: –92 dBFS
– No Input SNR: 71.1 dBFS
• Power Dissipation: 584 mW
• Performance Rated up to 105°C (at thermal pad)
• JESD204B Subclass 1 Single Lane Serial Data
Interface With Lane Rate Up To 5 Gb/s
• Buffered Analog Inputs
• Differential Input Phase and Amplitude Correction
• Input Sampling Clock Divider (Divide-by-1,2,4,8)
• 4-Wire Serial Peripheral Interface (SPI)
• 32-Pin WQFN Package (5×5 mm, 0.5-mm Pitch)
2 Applications
• High IF Sampling Receivers
• Multi-Carrier Base Station Receivers
– GSM/EDGE, CDMA2000, UMTS, LTE, WiMax
• Diversity, Multi-Mode, and Multiband Receivers
• Digital Pre-Distortion
• Software Defined Radio (SDR)
• Test and Measurement Equipment
• Communications Instrumentation
• Radar
• Portable Instrumentation
SPACE
1-Tone Spectrum, Input 240 MHz –3 dBFS
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
25
50
75
100
125
Frequency [MHz]
1
3 Description
The ADC14X250 device is a monolithic single-
channel high performance analog-to-digital converter
capable of converting analog input signals into 14-bit
digital words with a sampling rate of 250 MSPS. This
converter uses a differential pipelined architecture
with integrated input buffer to provide excellent
dynamic performance and low power consumption
across an extended temperature range from –40°C to
105°C as measured at the device's PCB footprint
thermal pad.
The integrated input buffer eliminates charge
kickback noise coming from the internal switched
capacitor sampling circuits and eases the system-
level design of the driving amplifier, anti-aliasing filter,
and impedance matching. The buffer can be also be
adjusted to correct for phase and amplitude
imbalance of the differential input signal path to
improve even order harmonic distortion. An input
sampling clock divider provides integer divide ratios
to simplify system clocking. An integrated low-noise
voltage reference eases board level design without
requiring external decoupling capacitors. The output
digital data is provided through a JESD204B subclass
1 single lane interface from a 32-pin, 5-mm × 5-mm
WQFN package. The ADC14X250 operates on 1.2 V,
1.8 V and 3.0 V power supplies. A SPI is available to
configure the device that is compatible with 1.2-V to
3-V logic.
PART NAME
ADC14X250
Device Information⁽¹⁾
PACKAGE
BODY SIZE (NOM)
WQFN (32)
5.00 × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Performance Stability Across Temperature (240 MHz)
110
SNR [dBFS]
105
SINAD [dBFS]
100
SFDR [dBFS]
95
90
85
80
75
70
65
60
-40 -20
0
20 40 60
Temperature [qC]
80 100
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.