ADC10D020_15 Datasheet, PDF (29/39 Pages) Texas Instruments – ADC10D020 Dual 10-Bit, 20 MSPS, 150 mW A/D Converter

ADC10D020
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SNAS143D – SEPTEMBER 2001 – REVISED MARCH 2013
As mentioned in the previous section, the V_CMO output can be used as the ADC reference.
V_CMO OUTPUT
The V_CMO output pin is intended to provide a common mode bias for the differential input pins of the
ADC10D020. It can also be used as a voltage reference source. Care should be taken, however, to avoid loading
this pin with more than 1 mA. A load greater than this could result in degraded long term and temperature
stability of this voltage. The V_CMO pin is output compensated and should be bypassed with a 2 µF/0.1 µF
combination, minimum. See REFERENCE INPUTS for more information on using the V_CMO output as a reference
source.
DIGITAL INPUT PINS
The seven digital input pins are used to control the function of the ADC10D020.
CLOCK (CLK) INPUT
The clock (CLK) input is common to both A/D converters. This pin is CMOS/LVTTL compatible with a threshold
of about V_A/2. Although the ADC10D020 is tested and its performance is specified with a 20 MHz clock, it
typically will function well with low-jitter clock frequencies from 1 MHz to 30 MHz. The clock source should be
series terminated to match the source impedance with the characteristic impedance, Z_O, of the clock line and the
ADC clock pin should be AC terminated, near the clock input, with a series RC to ground. The resistor value
should equal the characteristic impedance, Z_O, of the clock line and the capacitor should have a value such that
C × Z_O ≥ 4 × t_PD, where t_PD is the time of propagation of the clock signal from its source to the ADC clock pin.
The typical propagation rate on a board of FR4 material is about 150 ps/inch. The rise and fall times of the clock
supplied to the ADC clock pin should be no more than 4 ns. The analog inputs I = (I+) – (I−) and Q = (Q+) – (Q−)
are simultaneously sampled on the falling edge of this input to ensure the best possible aperture delay match
between the two channels.
OUTPUT BUS SELECT (OS) PIN
The Output Bus Select (OS) pin determines whether the ADC10D020 is in the parallel or multiplexed mode of
operation. A logic high at this pin puts the device into the parallel mode of operation where “I” and “Q” data
appear at their respective output buses. A logic low at this pin puts the device into the multiplexed mode of
operation where the “I” and “Q” data are multiplexed onto the “I” output bus and the “Q” output lines all remain at
a logic low.
OFFSET CORRECT (OC) PIN
The Offset Correct (OC) pin is used to initiate an offset correction sequence. This procedure should be done
after power up and need not be performed again unless power to the ADC10D020 is interrupted. An independent
offset correction sequence for each converter is initiated when there is a low-to-high transition at the OC pin. This
sequence takes 34 clock cycles to complete, during which time 32 conversions are taken and averaged. The
result is subtracted from subsequent conversions. Because the offset correction is performed digitally at the
output of the ADC, the output range of the ADC is reduced by the offset amount.
Upon power up, the offset correction coefficients are set to zero. The Electrical Table indicates the Offset Error
with and without performing an offset correction.
Each input pair should have a 0V differential voltage value during this entire 34 clock period, but the “I” and “Q”
input common mode voltages do not have to be equal to each other. Because of the uncertainty as to exactly
when the correction sequence starts, it is best to allow 35 clock periods for this sequence.
OUTPUT FORMAT (OF) PIN
The Output Format (OF) pin provides a choice of offset binary or 2's complement output formatting. With this pin
at a logic low, the output format is offset binary. With this pin at a logic high, the output format is 2's complement.
STANDBY (STBY) PIN
The Standby (STBY) pin may be used to put the ADC10D020 into a low power mode where it consumes just 27
mW and can quickly be brought to full operation. In this mode, most of the ADC10D020 is powered down, but the
bias and reference circuitry remained powered up to allow for a faster recovery from a low power standby
condition. The device operates normally with a logic low on this and the PD pins.
Copyright © 2001–2013, Texas Instruments Incorporated
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