ADC101C021_14 Datasheet, PDF (28/44 Pages) Texas Instruments – I2C-Compatible, 10-Bit Analog-to-Digital Converter (ADC) with Alert Function

ADC101C021, ADC101C027
SNAS446D – FEBRUARY 2008 – REVISED FEBRUARY 2013
www.ti.com
Reading from a 2-Byte ADC Register
The following diagrams indicate the sequence of actions required for a 2-Byte read from an ADC101C021
Register.
1
91
91
9
SCL
SDA
A6 A5 A4 A3 A2 A1 A0 R/W
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
Start by
Master
Frame 1
Address Byte
from Master
ACK
by
ADC
Frame 2
Data Byte from
ADC
ACK
by
Master
Frame 3
Data Byte from
ADC
N/ACK* Stop
by
by
Master Master
Repeat Frames
2 & 3 for
Continuous Mode
*Note: In continuous mode, this bit must be an ACK. Immediately
preceding a STOP condition, this bit must be a NACK.
Figure 26. Typical Read from a 2-Byte ADC Register with Preset Pointer
1
91
9
SCL
SDA
A6 A5 A4 A3 A2 A1 A0 R/W
0 0 0 0 0 P2 P1 P0
Start by
Master
Frame 1
Address Byte
from Master
Ack
by
ADC
Frame 2
Pointer Byte
from Master
Ack
by
ADC
SCL
(continued)
SDA
(continued)
1
91
91
9
A6 A5 A4 A3 A2 A1 A0 R/W
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
Repeat
ACK
ACK
N/ACK* Stop
Start by
by
by
by
by
Master
Frame 3
ADC
Frame 4
Master
Frame 5
Master Master
Address Byte
Data Byte from
Data Byte from
from Master
ADC
ADC
Repeat Frames
4 & 5 for
Continuous Mode
*Note: In continuous mode, this bit must be an ACK. Immediately
preceding a STOP condition, this bit must be a NACK.
Figure 27. Typical Pointer Set Followed by Immediate Read of a 2-Byte ADC Register
28
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: ADC101C021 ADC101C027