ADC101C021_14 Datasheet, PDF (15/44 Pages) Texas Instruments – I2C-Compatible, 10-Bit Analog-to-Digital Converter (ADC) with Alert Function

ADC101C021, ADC101C027
www.ti.com
SNAS446D – FEBRUARY 2008 – REVISED FEBRUARY 2013
FUNCTIONAL DESCRIPTION
The ADC101C021 is a successive-approximation analog-to-digital converter designed around a charge-
redistribution digital-to-analog converter. Unless otherwise stated, references to the ADC101C021 in this section
will apply to both the ADC101C021 and the ADC101C027.
CONVERTER OPERATION
Simplified schematics of the ADC101C021 in both track and hold modes are shown in Figure 17 and Figure 18,
respectively. In Figure 17, the ADC101C021 is in track mode. SW1 connects the sampling capacitor to the
analog input channel and SW2 equalizes the comparator inputs. The ADC is in this state for approximately 0.4µs
at the beginning of every conversion cycle, which begins at the ACK fall of SDA. Conversions occur when the
conversion result register is read and when the ADC is in automatic conversion mode. (see Section AUTOMATIC
CONVERSION MODE).
Figure 18 shows the ADC101C021 in hold mode. SW1 connects the sampling capacitor to ground and SW2
unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add or subtract
fixed amounts of charge to or from the sampling capacitor until the comparator is balanced. When the
comparator is balanced, the digital word supplied to the DAC is also the digital representation of the analog input
voltage. This digital word is stored in the conversion result register and read via the 2-wire interface.
In the Normal (non-Automatic) Conversion mode, a new conversion is started after the previous conversion result
is read. In the Automatic Mode, conversions are started at set intervals, as determined by bits D7 through D5 of
the Configuration Register. The intent of the Automatic mode is to provide a "watchdog" function to ensure that
the input voltage remains within the limits set in the Alert Limit Registers. The minimum and maximum
conversion results can then be read from the Lowest Conversion Register and the Highest Conversion Register,
as described in Section INTERNAL REGISTERS.
V_IN
SW1
SAMPLING
CAPACITOR
SW2
CHARGE
REDISTRIBUTION
DAC
+
CONTROL
-
LOGIC
AGND
V_A/2
Figure 17. ADC101C021 in Track Mode
V_IN
SW1
SAMPLING
CAPACITOR
CHARGE
REDISTRIBUTION
DAC
+
-
SW2
CONTROL
LOGIC
AGND
V_A/2
Figure 18. ADC101C021 in Hold Mode
ANALOG INPUT
An equivalent circuit for the input of the ADC101C021 is shown in Figure 19. The diodes provide ESD protection
for the analog input. The operating range for the analog input is 0 V to V_A. Going beyond this range will cause
the ESD diodes to conduct and may result in erratic operation. For this reason, these diodes should NOT be
used to clamp the input signal.
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